Intel® Xeon® Processor 5600 Series
23
Specification Update, March 2010
Management Mode) may cause the lower two bits of CS segment register to be
corrupted.
Implication:
The corruption of the bottom two bits of the CS segment register will have no impact
unless software explicitly examines the CS segment register between enabling
protected mode and
the first FAR JMP. Intel® 64 and IA-32 Architectures Software
Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section
titled "Switching to Protected Mode" recommends the FAR JMP immediately follows the
write to CR0 to enable protected mode. Intel has not observed this erratum with any
commercially available software.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD19.
A VM Exit on MWAIT May Incorrectly Report the Monitoring Hardware
as Armed
Problem:
A processor write to the address range armed by the MONITOR instruction may not
immediately trigger the monitoring hardware. Consequently, a VM exit on a later
MWAIT may incorrectly report the monitoring hardware as armed, when it should be
reported as unarmed due to the write occurring prior to the MWAIT.
Implication:
If a write to the range armed by the MONITOR instruction occurs between the
MONITOR and the MWAIT, the MWAIT instruction may start executing before the
monitoring hardware is triggered. If the MWAIT instruction causes a VM exit, this could
cause its exit qualification to incorrectly report 0x1. In the recommended usage model
for MONITOR/MWAIT, there is no write to the range armed by the MONITOR instruction
between the MONITOR and the MWAIT.
Workaround:
Software should never write to the address range armed by the MONITOR instruction
between the MONITOR and the subsequent MWAIT.
Status:
For the steppings affected, see the
BD20.
Performance Monitor Event SEGMENT_REG_LOADS Counts
Inaccurately
Problem:
The performance monitor event SEGMENT_REG_LOADS (Event 06H) counts
instructions that load new values into segment registers. The value of the count may be
inaccurate.
Implication:
The performance monitor event SEGMENT_REG_LOADS may reflect a count higher or
lower than the actual number of events.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD21.
#GP on Segment Selector Descriptor that Straddles Canonical
Boundary May Not Provide Correct Exception Error Code
Problem:
During a #GP (General Protection Exception), the processor pushes an error code on to
the exception handler’s stack. If the segment selector descriptor straddles the
canonical boundary, the error code pushed onto the stack may be incorrect.
Implication:
An incorrect error code may be pushed onto the stack. Intel has not observed this
erratum with any commercially available software.
Workaround:
None identified.
Status:
