Intel® Xeon® Processor 5600 Series
19
Specification Update, March 2010
Workaround:
None identified.
Status:
For the steppings affected, see the
BD4.
Performance Monitor SSE Retired Instructions May Return Incorrect
Values
Problem:
Performance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is used to track
retired SSE instructions. Due to this erratum, the processor may also count other types
of instructions resulting in higher than expected values.
Implication:
Performance Monitoring counter SIMD_INST_RETIRED may report count higher than
expected.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD5.
Premature Execution of a Load Operation Prior to Exception Handler
Invocation
Problem:
If any of the below circumstances occur, it is possible that the load portion of the
instruction will have executed before the exception handler is entered.
• If an instruction that performs a memory load causes a code segment limit
violation.
• If a waiting X87 floating-point (FP) instruction or MMX™ technology (MMX)
instruction that performs a memory load has a floating-point exception pending.
• If an MMX or SSE/SSE2/SSE3/SSSE3 extensions (SSE) instruction that performs a
memory load and has either CR0.EM=1 (Emulation bit set), or a floating-point Top-
of-Stack (FP TOS) not equal to 0, or a DNA exception pending.
Implication:
In normal code execution where the target of the load operation is to write back
memory there is no impact from the load being prematurely executed, or from the
restart and subsequent re-execution of that instruction by the exception handler. If the
target of the load is to uncached memory that has a system side-effect, restarting the
instruction may cause unexpected system behavior due to the repetition of the side-
effect. Particularly, while CR0.TS [bit 3] is set, a MOVD/MOVQ with MMX/XMM register
operands may issue a memory load before getting the DNA exception.
Workaround:
Code which performs loads from memory that has side-effects can effectively
workaround this behavior by using simple integer-based load instructions when
accessing side-effect memory and by ensuring that all code is written such that a code
segment limit violation cannot occur as a part of reading from side-effect memory.
Status:
For the steppings affected, see the
BD6.
MOV To/From Debug Registers Causes Debug Exception
Problem:
When in V86 mode, if a MOV instruction is executed to/from a debug registers, a
general-protection exception (#GP) should be generated. However, in the case when
the general detect enable flag (GD) bit is set, the observed behavior is that a debug
exception (#DB) is generated instead.
Implication:
With debug-register protection enabled (i.e., the GD bit set), when attempting to
execute a MOV on debug registers in V86 mode, a debug exception will be generated
instead of the expected general-protection fault.
Workaround:
In general, operating systems do not set the GD bit when they are in V86 mode. The
GD bit is generally set and used by debuggers. The debug exception handler should
check that the exception did not occur in V86 mode before continuing. If the exception
