Intel® Xeon® Processor 5600 Series
24
Specification Update, March 2010
BD22.
Improper Parity Error Signaled in the IQ Following Reset When a Code
Breakpoint is Set on a #GP Instruction
Problem:
While coming out of cold reset or exiting from C6, if the processor encounters an
instruction longer than 15 bytes (which causes a #GP) and a code breakpoint is
enabled on that instruction, an IQ (Instruction Queue) parity error may be incorrectly
logged resulting in an MCE (Machine Check Exception).
Implication:
When this erratum occurs, an MCE may be incorrectly signaled.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD23.
An Enabled Debug Breakpoint or Single Step Trap May Be Taken after
MOV SS/POP SS Instruction if it is Followed by an Instruction That
Signals a Floating Point Exception
Problem:
A MOV SS/POP SS instruction should inhibit all interrupts including debug breakpoints
until after execution of the following instruction. This is intended to allow the sequential
execution of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without having an
invalid stack during interrupt handling. However, an enabled debug breakpoint or single
step trap may be taken after MOV SS/POP SS if this instruction is followed by an
instruction that signals a floating point exception rather than a MOV [r/e]SP, [r/e]BP
instruction. This results in a debug exception being signaled on an unexpected
instruction boundary since the MOV SS/POP SS and the following instruction should be
executed atomically.
Implication:
This can result in incorrect signaling of a debug exception and possibly a mismatched
Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]SP,
[r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any
exception. Intel has not observed this erratum with any commercially available
software or system.
Workaround:
As recommended in the Intel® 64 and IA-32 Intel® Architectures Software Developer’s
Manual, the use of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP will avoid
the failure since the MOV [r/e]SP, [r/e]BP will not generate a floating point exception.
Developers of debug tools should be aware of the potential incorrect debug event
signaling created by this erratum.
Status:
For the steppings affected, see the
BD24.
IA32_MPERF Counter Stops Counting During On-Demand TM1
Problem:
According to the Intel® 64 and IA-32 Architectures Software Developer’s Manual
Volume 3A: System Programming Guide, the ratio of IA32_MPERF (MSR E7H) to
IA32_APERF (MSR E8H) should reflect actual performance while TM1 or on-demand
throttling is activated. Due to this erratum, IA32_MPERF MSR stops counting while TM1
or on-demand throttling is activated, and the ratio of the two will indicate higher
processor performance than actual.
Implication:
The incorrect ratio of IA32_APERF/IA32_MPERF can mislead software P-state
(performance state) management algorithms under the conditions described above. It
is possible for the Operating System to observe higher processor utilization than actual,
which could lead the OS into raising the P-state. During TM1 activation, the OS P-state
request is irrelevant and while on-demand throttling is enabled, it is expected that the
OS will not be changing the P-state. This erratum should result in no practical
implication to software.
Workaround:
None identified.
Status:
