A.7. Intel MAX 10 SPI Bus
The Intel MAX 10 device uses the SPI bus for reading telemetry information from the
Analog Devices LTC3888 VCC core controller.
Table 39.
SPI Signals
Schematic Signal Name
FPGA Pin Number
I/O Standard
Description
LTC_1V8_SDI
L2
1.8 V CMOS
SPI data
LTC_1V8_SCK
N2
1.8 V CMOS
SPI clock
LTC_1V8_SPI_ERRn
M1
1.8 V CMOS
SPI error status
LTC_1V8_SCSn
P1
1.8 V CMOS
SPI chip select
A.8. Clock Circuits
Figure 26.
Intel Agilex F-Series FPGA Development Kit Clocks and Default Frequencies
CXL
Conn
(J9)
PCIe
Gold
Finger
(J1)
Si52204
(U25)
Si53254A
(U27)
ZL30733
IEEE
1588
Clock
(U23)
1
2
Agilex
FPGA
(U8)
25 MHz
Y1
OSC
125 MHz
PPS_FPGA_clkout
ToD_master_clk_125M_P/N (125 MHz)
clk_FPGA_100M_P/N (100 MHz)
PTP_sample_clk_250M_P/N (250 MHz)
DDR4_DIMM1_refclk_P/N (166.625 MHz)
DDR4_DIMM2_refclk_P/N (166.625 MHz)
DDR4_comp_refclk_P/N (166.625 MHz)
QSFPDD_refclk_P/N (156.25 MHz)
QSFP_refclk_P/N (156.25 MHz)
CIPRI_high_P/N (184.32 MHz)
CIPRI_low_P/N (153.6 MHz)
FPGA_rcvd_clk1_REFOUT_P/N
FPGA_rcvd_clk2_REFOUT_P/N
clk_CXL_conn_P/N (100 MHz)
Refclk_CXL_conn_P/N
Refclk_CXL_EP_P/N
FPGA_OSC_clk1
Refclk_PCIe_13A_ch2_P/N
Refclk_CXL_RP_P/N (100 MHz)
Clk_CXL_EP_P/N (100 MHz)
Refclk_PCIe_EP_P/N (100 MHz)
Refclk_PCIe_EP_EDGE_P/N (100 MHz)
Refclk_PCIe_13A_ch5_P/N
Bank3A
Bank12C
Bank2C
Bank2F
Bank3D
SDM
Bank13A
Si53254A
(U26)
2
1
A. Development Kit Components
739942 | 2022.09.21
Intel
®
Agilex
™
F-Series FPGA (Two F-Tiles) Development Kit User Guide
63
