Intel Agilex F Series, User Manual

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Board Reference Type Description
• 32 x 32 Gbps Transceivers
• 24 x 58Gbps Transceivers
• 2340 pin BGA Package
U5 CPLD Intel MAX 10 CPLD, 10M50DAF256I7G
Table 9. Configuration and Setup Elements
Board
Reference
Type Description
J10 On-board Intel FPGA Download
Cable II
Micro-USB 2.0 connector for programming and debugging the
FPGA.
SW1 PCIe control DIP switch Enables PCIe link widths x1, x4, x8, and x16.
SW2 Intel FPGA Download Cable II
selection switch
Selects between the on-board Intel FPGA Download Cable II or
external Intel FPGA Download Cable II connected to J3 header.
SW3
Position 1-2 JTAG bypass DIP switch Enables and disables devices in the JTAG chain.
SW3 Position
3-4
MSEL configuration DIP switch Sets the Intel Agilex MSEL configuration modes
SW4 PCIe clock control DIP switch Provides control for PCIe clock controls such as Spread Spectrum
enable/disable, local or external PCIe clock source, and PCIe
REFCLK power down.
SW5 Power-on slide switch Main switch for powering on the Board when used in bench-top
mode. This switch is ignored when the board is used in a PCIe
system.
SW6 Intel MAX 10 JTAGEN switch Enables Intel MAX 10 to use the JTAG pins as I/Os.
S1 CPU RESETn Sends an active low signal to the FPGA and Intel MAX 10 which can
be used as the RESET for internal designs.
S2 HPS RESETn Sends an active low signal to the Intel MAX 10. Intel MAX 10 can
then send HPS_DC_RSTn to the HPS IO48 daughter card is
present.
S3 1st_PCIe_PERSTN push-button Sends an active low signal to the dedicated PCIe_PERSTN pin of
transceiver Bank 13A.
S4 2nd_PCIe_PERSTN push-button Sends an active low signal to a GPIO pin in Bank 3A. This pin can
be used as a secondary PERSTN signal.
S6 CXL_PCIe_PERSTN push-button Sends an active low signal to the CXL connector PERSTN pin.
J105 Configuration image selection Use together with J106 to select image stored in U4 for Avalon-ST
x16.
J106 Configuration image selection Use together with J105 to select image stored in U4 for Avalon-ST
x16.
Table 10. Status Elements
Board Reference Type Description
D1 Green Intel MAX 10 CONF_DONE
LED
LED is on when the Intel MAX 10 is successfully configured.
D2 Blue power good LED LED is on when Intel MAX 10 detects that all power on the board
is good.
continued...
A. Development Kit Components
739942 | 2022.09.21
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F-Series FPGA (Two F-Tiles) Development Kit User Guide
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