Intel Agilex F Series, User Manual

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Schematic Signal Name FPGA Pin Number I/O Standard Description
DDR4_DIMM1_DQ37 DF22 1.2 V HS LVCMOS DDR4 DIMM1 DQ37 data
DDR4_DIMM1_DQ38 DJ23 1.2 V HS LVCMOS DDR4 DIMM1 DQ38 data
DDR4_DIMM1_DQ39 DH22 1.2 V HS LVCMOS DDR4 DIMM1 DQ39 data
DDR4_DIMM1_DQS_P4 DH24 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Positive for byte lane 4
DDR4_DIMM1_DQS_N4 DJ25 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Negative for byte lane 4
DDR4_DIMM1_DBI_N4 DF24 1.2 V HS LVCMOS DDR4 DIMM1 Data Bus Inversion for byte lane 4
DDR4_DIMM1_TDQS_N13 DE25 1.2 V HS LVCMOS DDR4 DIMM1 Termination Data Strobe for byte lane 4
DDR4_DIMM1_DQ40 DC19 1.2 V HS LVCMOS DDR4 DIMM1 DQ40 data
DDR4_DIMM1_DQ41 DD18 1.2 V HS LVCMOS DDR4 DIMM1 DQ41 data
DDR4_DIMM1_DQ42 CY18 1.2 V HS LVCMOS DDR4 DIMM1 DQ42 data
DDR4_DIMM1_DQ43 DA19 1.2 V HS LVCMOS DDR4 DIMM1 DQ43 data
DDR4_DIMM1_DQ44 CY14 1.2 V HS LVCMOS DDR4 DIMM1 DQ44 data
DDR4_DIMM1_DQ45 DA15 1.2 V HS LVCMOS DDR4 DIMM1 DQ45 data
DDR4_DIMM1_DQ46 DC15 1.2 V HS LVCMOS DDR4 DIMM1 DQ46 data
DDR4_DIMM1_DQ47 DD14 1.2 V HS LVCMOS DDR4 DIMM1 DQ47 data
DDR4_DIMM1_DQS_P5 DD16 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Positive for byte lane 5
DDR4_DIMM1_DQS_N5 DC17 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Negative for byte lane 5
DDR4_DIMM1_DBI_N5 CY16 1.2 V HS LVCMOS DDR4 DIMM1 Data Bus Inversion for byte lane 5
DDR4_DIMM1_TDQS_N14 DA17 1.2 V HS LVCMOS DDR4 DIMM1 Termination Data Strobe for byte lane 5
DDR4_DIMM1_DQ48 CY24 1.2 V HS LVCMOS DDR4 DIMM1 DQ48 data
DDR4_DIMM1_DQ49 DD24 1.2 V HS LVCMOS DDR4 DIMM1 DQ49 data
DDR4_DIMM1_DQ50 DC25 1.2 V HS LVCMOS DDR4 DIMM1 DQ50 data
DDR4_DIMM1_DQ51 DA25 1.2 V HS LVCMOS DDR4 DIMM1 DQ51 data
DDR4_DIMM1_DQ52 CY20 1.2 V HS LVCMOS DDR4 DIMM1 DQ52 data
DDR4_DIMM1_DQ53 DC21 1.2 V HS LVCMOS DDR4 DIMM1 DQ53 data
DDR4_DIMM1_DQ54 DA21 1.2 V HS LVCMOS DDR4 DIMM1 DQ54 data
DDR4_DIMM1_DQ55 DD20 1.2 V HS LVCMOS DDR4 DIMM1 DQ55 data
DDR4_DIMM1_DQS_P6 DD22 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Positive for byte lane 6
DDR4_DIMM1_DQS_N6 DC23 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Negative for byte lane 6
DDR4_DIMM1_DBI_N6 CY22 1.2 V HS LVCMOS DDR4 DIMM1 Data Bus Inversion for byte lane 6
continued...
A. Development Kit Components
739942 | 2022.09.21
Intel
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Agilex
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F-Series FPGA (Two F-Tiles) Development Kit User Guide
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