
Schematic Signal Name
FPGA Pin Number
I/O Standard
Description
Negative, Remote board clock
CXL_PERSTN
D43
1.2 V HS LVCMOS
CXL Reset
CXL_PRSNTx4_N
F50
1.2 V HS LVCMOS
CXL Present
A.5.5. DDR4 DIMM1 Interface
The Intel Agilex FPGA (two F-tiles) development board provides two DDR4 x72 DIMM
interfaces connected to the FPGA fabric. DIMM1 is connected to the Intel Agilex I/O96
of banks 2C and 2D. Only one DIMM memory module is included with the development
kit for evaluation of the DDR4 interfaces.
Table 33.
DIMM1 Pin Assignments
Schematic Signal Name FPGA Pin Number
I/O Standard
Description
DDR4_DIMM1_DQ0
DC31
1.2 V HS LVCMOS
DDR4 DIMM1 DQ0 data
DDR4_DIMM1_DQ1
DD30
1.2 V HS LVCMOS
DDR4 DIMM1 DQ1 data
DDR4_DIMM1_DQ2
CY30
1.2 V HS LVCMOS
DDR4 DIMM1 DQ2 data
DDR4_DIMM1_DQ3
DA31
1.2 V HS LVCMOS
DDR4 DIMM1 DQ3 data
DDR4_DIMM1_DQ4
DA27
1.2 V HS LVCMOS
DDR4 DIMM1 DQ4 data
DDR4_DIMM1_DQ5
CY26
1.2 V HS LVCMOS
DDR4 DIMM1 DQ5 data
DDR4_DIMM1_DQ6
DC27
1.2 V HS LVCMOS
DDR4 DIMM1 DQ6 data
DDR4_DIMM1_DQ7
DD26
1.2 V HS LVCMOS
DDR4 DIMM1 DQ7 data
DDR4_DIMM1_DQS_P0
DD28
1.2 V HS LVCMOS
DDR4 DIMM1 Data Strobe
Positive for byte lane 0
DDR4_DIMM1_DQS_N0
DC29
1.2 V HS LVCMOS
DDR4 DIMM1 Data Strobe
Negative for byte lane 0
DDR4_DIMM1_DBI_N0
CY28
1.2 V HS LVCMOS
DDR4 DIMM1 Data Bus Inversion for byte lane 0
DDR4_DIMM1_TDQS_N9
DA29
1.2 V HS LVCMOS
DDR4 DIMM1 Termination Data Strobe for byte lane 0
DDR4_DIMM1_DQ8
DF20
1.2 V HS LVCMOS
DDR4 DIMM1 DQ8 data
DDR4_DIMM1_DQ9
DJ21
1.2 V HS LVCMOS
DDR4 DIMM1 DQ9 data
DDR4_DIMM1_DQ10
DH20
1.2 V HS LVCMOS
DDR4 DIMM1 DQ10 data
DDR4_DIMM1_DQ11
DE21
1.2 V HS LVCMOS
DDR4 DIMM1 DQ11 data
DDR4_DIMM1_DQ12
DF16
1.2 V HS LVCMOS
DDR4 DIMM1 DQ12 data
DDR4_DIMM1_DQ13
DH16
1.2 V HS LVCMOS
DDR4 DIMM1 DQ13 data
DDR4_DIMM1_DQ14
DE17
1.2 V HS LVCMOS
DDR4 DIMM1 DQ14 data
DDR4_DIMM1_DQ15
DJ17
1.2 V HS LVCMOS
DDR4 DIMM1 DQ15 data
DDR4_DIMM1_DQS_P1
DH18
1.2 V HS LVCMOS
DDR4 DIMM1 Data Strobe
Positive for byte lane 1
DDR4_DIMM1_DQS_N1
DJ19
1.2 V HS LVCMOS
DDR4 DIMM1 Data Strobe
continued...
A. Development Kit Components
739942 | 2022.09.21
Intel
®
Agilex
™
F-Series FPGA (Two F-Tiles) Development Kit User Guide
48