Intel Agilex F Series, User Manual

Page: 54 / 75

Schematic Signal Name FPGA Pin Number I/O Standard Description
DDR4_DIMM2_DQ23 CR53 1.2 V HS LVCMOS DDR4 DIMM2 DQ23 data
DDR4_DIMM2_DQS_P2 CP50 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Positive for byte lane 2
DDR4_DIMM2_DQS_N2 CN51 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Negative for byte lane 2
DDR4_DIMM2_DBI_N2 CK50 1.2 V HS LVCMOS DDR4 DIMM2 Data Bus Inversion for byte lane 2
DDR4_DIMM2_TDQS_N11 CL51 1.2 V HS LVCMOS DDR4 DIMM2 Termination Data Strobe for byte lane 2
DDR4_DIMM2_DQ24 CR47 1.2 V HS LVCMOS DDR4 DIMM2 DQ24 data
DDR4_DIMM2_DQ25 CT46 1.2 V HS LVCMOS DDR4 DIMM2 DQ25 data
DDR4_DIMM2_DQ26 CV46 1.2 V HS LVCMOS DDR4 DIMM2 DQ26 data
DDR4_DIMM2_DQ27 CW47 1.2 V HS LVCMOS DDR4 DIMM2 DQ27 data
DDR4_DIMM2_DQ28 CW43 1.2 V HS LVCMOS DDR4 DIMM2 DQ28 data
DDR4_DIMM2_DQ29 CV42 1.2 V HS LVCMOS DDR4 DIMM2 DQ29 data
DDR4_DIMM2_DQ30 CR43 1.2 V HS LVCMOS DDR4 DIMM2 DQ30 data
DDR4_DIMM2_DQ31 CT42 1.2 V HS LVCMOS DDR4 DIMM2 DQ31 data
DDR4_DIMM2_DQS_P3 CV44 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Positive for byte lane 3
DDR4_DIMM2_DQS_N3 CW45 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Negative for byte lane 3
DDR4_DIMM2_DBI_N3 CT44 1.2 V HS LVCMOS DDR4 DIMM2 Data Bus Inversion for byte lane 3
DDR4_DIMM2_TDQS_N12 CR45 1.2 V HS LVCMOS DDR4 DIMM2 Termination Data Strobe for byte lane 3
DDR4_DIMM2_DQ32 CV48 1.2 V HS LVCMOS DDR4 DIMM2 DQ32 data
DDR4_DIMM2_DQ33 CT48 1.2 V HS LVCMOS DDR4 DIMM2 DQ33 data
DDR4_DIMM2_DQ34 CW49 1.2 V HS LVCMOS DDR4 DIMM2 DQ34 data
DDR4_DIMM2_DQ35 CR49 1.2 V HS LVCMOS DDR4 DIMM2 DQ35 data
DDR4_DIMM2_DQ36 CW53 1.2 V HS LVCMOS DDR4 DIMM2 DQ36 data
DDR4_DIMM2_DQ37 CV52 1.2 V HS LVCMOS DDR4 DIMM2 DQ37 data
DDR4_DIMM2_DQ38 CW55 1.2 V HS LVCMOS DDR4 DIMM2 DQ38 data
DDR4_DIMM2_DQ39 CV54 1.2 V HS LVCMOS DDR4 DIMM2 DQ39 data
DDR4_DIMM2_DQS_P4 CV50 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Positive for byte lane 4
DDR4_DIMM2_DQS_N4 CW51 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Negative for byte lane 4
DDR4_DIMM2_DBI_N4 CT50 1.2 V HS LVCMOS DDR4 DIMM2 Data Bus Inversion for byte lane 4
DDR4_DIMM2_TDQS_N13 CR51 1.2 V HS LVCMOS DDR4 DIMM2 Termination Data Strobe for byte lane 4
DDR4_DIMM2_DQ40 CY50 1.2 V HS LVCMOS DDR4 DIMM2 DQ40 data
continued...
A. Development Kit Components
739942 | 2022.09.21
Intel
®
Agilex
™
F-Series FPGA (Two F-Tiles) Development Kit User Guide
Send Feedback
54