Board Reference
Type
Description
D28
LT1389 VREF generation
1.25V VREF for VCCBAT
U74
Intersil ISL80101
1.8V VCCIO_SDM_HPS LDO voltage regulator
U75
Intersil ISL80101
2.5V DDR4 DIMM LDO voltage regulator
U76
Intersil ISL80101
2.5V DDR4 COMP LDO voltage regulator
U77
Texas Instruments TPS51200
0.6V DDR4 DIMM VTT/VREF generation
U78
Texas Instruments TPS51200
0.6V DDR4 COMP VTT/VREF generation
A.1.3. Intel MAX 10 CPLD System Controller
The development board utilizes the 10M50 system controller, an Intel MAX 10 CPLD
for the following purposes:
•
Power sequencing control
•
FPGA configuration from flash memory
•
On-board Intel FPGA Download Cable II
•
Power monitoring
•
Temperature monitoring
•
Fan control
•
Clock control
A.2. FPGA Configuration
You can use the Intel Quartus Prime Programmer to configure the FPGA with your
SRAM Object File (.sof).
Ensure the following:
•
The Intel Quartus Prime Programmer and the Intel FPGA Download Cable II driver
are installed on the host computer.
•
The micro-USB cable is connected to the FPGA development board.
•
Power to the board is ON, and no other applications that use the JTAG chain are
running.
To configure the FPGA, follow these steps:
1. Start the Intel Quartus Prime Programmer.
2. Click Auto Detect to display the devices in the JTAG chain.
3. Click Change File and select the path to the desired .sof.
4. Turn on the Program/Configure option for the added file.
5. Click Start to download the selected file to the FPGA. Configuration is complete
when the progress bar reaches 100%.
A. Development Kit Components
739942 | 2022.09.21
Intel
®
Agilex
™
F-Series FPGA (Two F-Tiles) Development Kit User Guide
36
