Table 20.
Supported Configuration Modes
MSEL0
is tied to logic high.
Configuration Mode
MSEL2
MSEL1
MSEL0
JTAG
1
1
1
Avalon-ST x16
1
0
1
AS x4 Fast (CVP support)
0
0
1
AS x4 Normal
0
1
1
Table 21.
SW4
Switch position
Board Label
Function
Default Position
1
SSEN
ON enables PCIe Spread Spectrum
OFF
2
CXL REFCLK Select
ON for local PCIe REFCLK on Bank12C
OFF
3
PCIe REFCLK Select
ON for local PCIe REFCLK on Bank13A
OFF
4
PCIe Clock Power-down
On powers down PCIe clock sources
OFF
Table 22.
SW5—Slide Switch to Power On the Board
Switch position
Board Label
Function
Default Position
SW5
Power On
ON to power on the board
OFF
Table 23.
SW6—Single DIP for Intel MAX 10 JTAG Enable
Switch position
Board Label
Function
Default Position
SW6
Intel MAX 10 JTAG Enable
ON to share Intel MAX 10 JTAG Pins
OFF
Table 24.
S[1–4, 6]—Various Push-Button RESET Switches
Switch
Function
S1
Used to send RESET to CPU
S2
Used to send RESET to HPS
S3
Used to send PERSTN to PCIe
S4
Used to send 2nd PERSTN to PCIe
S6
Used to send PERSTN to CXL PCIe
A.3.2. Jumper Description
In Avalon-ST x16 configuration mode, the board provides one QSPI flash for storing up
to four configuration images. Configuration of the FPGA with one of these images is
managed by the Intel MAX 10, depending on the selection of jumpers J105 and J106.
A. Development Kit Components
739942 | 2022.09.21
Intel
®
Agilex
™
F-Series FPGA (Two F-Tiles) Development Kit User Guide
39
