Figure 25.
I
2
C Block Diagram
(S)
QSFPDD
(J7)
DIMM1
(J4)
ADDR=A0h
ADDR=A1h
ADDR=55h
MAX_12C_SCL/SDA
ADDR=42h
FX2_SCL/SDA
SPI Bus
FPGA_SCL/SDA
HPS_SCL/SDA
FPGA SVID to VCC Regulator
ADDR=4 Eh
ADDR=56h/5 Eh
DIMM2
(J5)
IOEXP
(U97)
M24128
CERT
EEPROM
(U46)
ModSelL
(S)
(M)
(M)
(M)
(M)
(M)
(M)
(S)
MAX 10
System Controller
(U5)
(S)
ADDR=40h
(M)
(S)
ADDR=A0h
PCI
e_3V3_EP_SMBCLK/SMBD
AT
PCIe
Gold Finger
(J1)
(M)
IO48
Daughter
Card
(S)
QSFD
(J8)
Agilex FPGA
(U8)
HPS IO48
(J6)
ModSelL
LTC3888-1
VCC,
VCC HSSI
(U61)
ADDR=70h
ZL30733
Clock
(U23)
(S)
ADDR=6Ah
Si52204
Clock
(U25)
(S)
ADDR=57h/5Fh
M24128
MAC
EEPROM
(U44)
(S)
ADDR=74h
LTC7132
VCCERT_FGT_GXF
VCCR_CORE
(U93)
(S)
ADDR=75h
LTC7132
VCCPT
VCCIO_1V2
(U96)
ADDR=38h
MAX31730
Temp Sense
(EU1)
ADDR=9Ah
MAX31730
Temp Sense
(EU2)
(S)
USB
Blaster
PHY
(U49)
(M)
MAX16545B
PCIe HSC
(U50)
(S)
(S)
MAX16545B
AUX HSC
(U54)
(S)
M24128
FRUID
(U2)
(S)
Table 37.
Intel MAX 10 I
2
C Signals
Schematic Signal Name
MAX Pin Number
I/O Standard
Description
MAX_I2C_SCL
J11
3.3 V open drain
Intel MAX 10 I
2
C clock
MAX_I2C_SDA
J12
3.3 V open drain
Intel MAX 10 I
2
C data
FX2_SCL
R1
3.3 V open drain
USB PHY I
2
C clock
FX2_SDA
R3
3.3 V open drain
USB PHY I
2
C data
Table 38.
FPGA I
2
C Signals
Schematic Signal Name FPGA Pin Number
I/O Standard
Description
FPGA_1V8_SVID_SCL
CG47
1.8 V open drain Serial voltage ID I
2
C clock
FPGA_1V8_SVID_SDA
CB46
1.8 V open drain Serial voltage ID I
2
C data
FPGA_1V2_SCL
K44
1.2 V open drain FPGA I
2
C clock for DDR4 DIMMs, QSFP, QSFPDD, IO
expander, and certificate EEPROM
FPGA_1V2_SDA
J43
1.2 V open drain FPGA I
2
C data for DDR4 DIMMs, QSFP, QSFPDD, IO
expander, and certificate EEPROM
HPS_SCL
N3
1.8 V open drain HPS I/O48 daughter card I
2
C clock
HPS_SDA
L6
1.8 V open drain HPS I/O48 daughter card I
2
C data
A. Development Kit Components
739942 | 2022.09.21
Intel
®
Agilex
™
F-Series FPGA (Two F-Tiles) Development Kit User Guide
62
