Figure 24.
Switch and Jumper Locations
SW5
SW3
SW2
J106 J105
Top Side of Board
SW6 S1 S2 S3 S4 S6
SW4
SW1
Agilex
FPGA
A.3.1. Switch Description
Table 17.
SW1—4 Position DIP for PCIe Lane Width Selection
Switch position
Board Label
Function
Default Position
1
x16
ON for PCIe x16
ON
2
x8
ON for PCIe x8
OFF
3
x4
ON for PCIe x4
OFF
4
x1
ON for PCIe x1
OFF
Table 18.
SW2—Single DIP for Intel FPGA Download Cable II Selection
Switch position
Board Label
Function
Default Position
SW2
USB MAX JTAG SEL
ON for on-board Intel FPGA Download Cable II
ON
OFF for external Intel FPGA Download Cable II
Table 19.
SW3—4 position DIP for Configuration Mode Selection and JTAG Control
By default,
MSEL[2:0]
is set to '001' for AS x4 with CvP support.
MSEL0
is tied to logic high.
Switch position
Board Label
Function
Default Position
1
MSEL1
Configuration MSEL1
ON
2
MSEL2
Configuration MSEL2
ON
3
BMC JTAG SEL
ON Selects On-board Blaster
ON
4
HPS JTAG BYPASS
OFF Bypass HPS JTAG
OFF
The board only supports the following configuration modes.
A. Development Kit Components
739942 | 2022.09.21
Intel
®
Agilex
™
F-Series FPGA (Two F-Tiles) Development Kit User Guide
38
