Intel Agilex F Series, User Manual

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A.5.4. CXL Interface
The Intel Agilex FPGA (two F-tiles) development board provides a CXL connector
interface for cabling to an Intel-designed M.2 SSD daughter card supporting M-Keying.
This interface connects to four 28 Gbps F-tile lanes of the Intel Agilex FPGA. When
connecting the development board to this SSD daughter card, the development board
connects four transceiver channels from the F-tile bank 12C to M2 channels 8-11 (J5)
of the M.2 daughter card.
Table 32. CXL Pin Assignments
Schematic Signal Name FPGA Pin Number I/O Standard Description
CXL_TX_P0 BW49 True Differential Signaling CXL Transmit Channel 0 Positive
CXL_TX_N0 BY48 True Differential Signaling CXL Transmit Channel 0 Negative
CXL_TX_P1 BV52 True Differential Signaling CXL Transmit Channel 1 Positive
CXL_TX_N1 BU51 True Differential Signaling CXL Transmit Channel 1 Negative
CXL_TX_P2 BR49 True Differential Signaling CXL Transmit Channel 2 Positive
CXL_TX_N2 BT48 True Differential Signaling CXL Transmit Channel 2 Negative
CXL_TX_P3 BP52 True Differential Signaling CXL Transmit Channel 3 Positive
CXL_TX_N3 BN51 True Differential Signaling CXL Transmit Channel 3 Negative
CXL_RX_P0 CC55 True Differential Signaling CXL Receive Channel 0
Positive
CXL_RX_N0 CD54 True Differential Signaling CXL Receive Channel 0 Negative
CXL_RX_P1 CB52 True Differential Signaling CXL Receive Channel 1
Positive
CXL_RX_N1 CA51 True Differential Signaling CXL Receive Channel 1 Negative
CXL_RX_P2 BW55 True Differential Signaling CXL Receive Channel 2
Positive
CXL_RX_N2 BY54 True Differential Signaling CXL Receive Channel 2 Negative
CXL_RX_P3 BR55 True Differential Signaling CXL Receive Channel 3
Positive
CXL_RX_N3 BT54 True Differential Signaling CXL Receive Channel 3 Negative
REFCLK_CXL_EP_P BC49 100 MHz LVPECL CXL Reference Clock
Positive, Local board clock
REFCLK_CXL_EP_N BE49 100 MHz LVPECL CXL Reference Clock
Negative, Local board clock
REFCLK_CXL_CONN_P BG49 100 MHz LVPECL CXL Reference Clock
Positive, Remote board clock
REFCLK_CLK_CONN_N BF48 100 MHz LVPECL CXL Reference Clock
continued...
A. Development Kit Components
739942 | 2022.09.21
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F-Series FPGA (Two F-Tiles) Development Kit User Guide
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