INGENIA Everest CORE, Product Manual

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Everest CORE - Product Manual | Application Guide
INGENIA | 08/01/2019 43
Signals description
Signal Description
+3.3V_D +3.3 V Logic supply
MCB_SPI_MIS
O Master input, Everest CORE output. To be connected to pin 14 of Everest CORE Interface
connector
MCB_SPI_MOS
I Master output, Everest CORE input. To be connected to pin 16 of Everest CORE Interface
connector
\MCB_SPI_CS Everest CORE chip select. To be connected to pin 18 of Everest CORE Interface connector
MCB_SPI_CLK Master clock output. To be connected to pin 20 of Everest CORE Interface connector
MCB_SYNC0 Synchronisation signal 0. To be connected to pin 22 of Everest CORE Interface connector
MCB_SYNC1 Synchronisation signal 1. To be connected to pin 24 of Everest CORE Interface connector
MCB_IRQ Everest CORE Interrupt Request output to Master. To be connected to pin 26 of Everest CORE
Interface connector
\HW_RESET Everest CORE Reset input. To be connected to pin 38 of Everest CORE Interface connector
GND_D Logic supply reference voltage. To be connected to pins from 13, 15, 17, 19, 21, 23 and 25 of
Everest CORE Interface connector
Design Notes
• MCB_SYNC1 and MCB_IRQ are used during boot-up; R1 and R2 ensure a proper boot-up sequence. Assuming
that the driving pins can be momentarily set in a high impedance state just at the starting point of the boot-
up, their voltage could be undefined without R1 and R2.
Bill of materials
Designa
tor Part Number Manufact
urer Package Value / Description
R1, R2 RMCF0402FT1
0K0 Stackpole 0402 Thick film resistor, 10 k Ω , 1 % tolerance, 1/16 W
Digital Halls
This circuit assume a typical open collector output from a digital hall circuitry and provides 5 V level pull-ups to
interface it. Then, a 1st order RC filter plus an Schmitt trigger buffer filter the signal and translates it to 3.3 V levels
for a decent ruggedness against noise.