Everest CORE - Product Manual |
Application Guide
INGENIA | 08/01/2019
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In the proposed layout, copper in Top layer is represented in red, Mid layer 1 is represented in yellow, Mid layer 2 in
blue and the rest of layers in green (some traces might be hidden in the image). This proposal also uses simple TH
vias sized to fit a very attainable Class 6 PCB manufacturing category. This is a quite average level of sophistication,
in terms of PCB manufacturing technology, but is sufficient to interface the Everest CORE, thus entailing a cheaper
cost. However, very dense designs might go for a less restrictive PCB Class, specially when most of the signals in the
mezzanine connectors are used.
Use of vias or microvias
Although not specifically required, designs where most of the signal pins are used at the same time may
consider interfacing the mezzanine connectors with in-pad microvias between Top and Mid 1 layers
instead of classical TH vias. Note that this might entail higher PCB manufacturing costs.
