Everest CORE - Product Manual |
Application Guide
INGENIA | 08/01/2019
48
Schematic
Signals description
Signal
Description
+3.3V_D
+3.3 V Logic supply
+5V_D
+5 V Logic supply
ABSENC_CLK_N
Clock output differential pair to absolute encoder
ABSENC_CLK_P
ABSENC_DATA_N Data input differential pair to absolute encoder
ABSENC_DATA_P
ABSENC_CLK
Clock signal from Everest CORE to be connected to pin 38 of Feedback connector or pin 50 of
Interface connector
ABSENC_DATA
Data signal from Everest CORE to be connected to pin 40 of Feedback connector or pin 51 of
Interface connector
GND_D
Logic supply reference voltage. To be connected to pin 36 of Feedback connector or either
pins 59 or 60 of Interface connector