IDT 89HPES16NT2, User Manual

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IDT Clocking, Reset, and Initialization Clock Operation
PES16NT2 User Manual 2 - 9 April 15, 2008
Notes
Globally Initiated Hot Reset To Downstream Ports
A hot reset is initiated globally to downstream ports when the following condition occurs:
– A one is written to the Secondary Bus Reset (SRESET) bit in the upstream port’s (port A) Bridge
Control Register (BCTRL).
When a globally initiated hot reset is initiated to downstream ports, all of the logic associated with the
transparent bridges, stacks and FIFOs in the switch core associated with the downstream ports are reset
except for the PLLs, SerDes, master SMBus interface, slave SMBus interface, and some registers. Regard-
less of the switch operating mode, it does not result in reloading of the serial EEPROM.
The value of register fields denoted as “sticky” or as Read and Write when Unlocked (i.e., RWL) in
downstream ports are preserved. All other register fields are reset to their initial values.
When a hot reset is initiated globally to downstream ports, each downstream port sends a hot-reset
message to its link partner prior to being reset. Unlike a globally initiated hot reset to the entire device, a
globally initiated hot reset to downstream ports does not affect the state of the upstream port’s configuration
register except those required to update port status.
Locally Initiated Hot Reset to a Downstream Port
A hot reset is initiated locally to a downstream port by writing to the SRESET bit of a downstream port’s
BCTRL registers. When this occurs, a hot-reset message is sent on that port to its link partner. After the
message is sent, the phy layer is effectively reset.
A locally initiated hot reset does not affect the state of any port (i.e., transparent bridge) configuration
register except those required to update port status.
Non-Transparent Mode Reset
Fundamental and hot resets may be initiated on both the internal side and external sides of the non-
transparent bridge. Associated with each side of the non-transparent bridge are control and status registers
(NTBCTL and NTBSTS) that aid in the handling of hot and fundamental resets in non-transparent modes.
The Reset Action Enable (RAEN) bit in the PCIE_NTBCTL register together with the Reset Action (RA)
field in that register allow a side (internal or external) of the non-transparent bridge to become “not ready”
when a reset is detected on the opposite side of the non-transparent bridge. This allows a root on one side
of the non-transparent bridge to configure the system before transactions are accepted on the opposite side
of the non-transparent bridge.
Internal Side Fundamental Reset
In non-transparent mode, a fundamental reset from the internal side operates as described in section
Fundamental Reset on page 2-7. An internal side fundamental reset resets all logic in the device including
both sides of the non-transparent bridge.
In addition to performing the actions outlined in that section, an internal side fundamental reset causes
the Opposite Side Mode (OSMODE) field in the PCIE_NTBCTL register to be set to opposite side not
ready. This disables accesses from the external side until the internal side root complex has configured the
non-transparent bridge.
If a system designer wishes to have the external side root complex initialize the non-transparent bridge,
then this can be achieved by initializing the state of the PCIE_NTBCTL and PCEE_NTBCTL registers via
the serial EEPROM.
External Side Fundamental Reset
An external side fundamental reset is initiated when the switch is configured to operate in non-trans-
parent mode and the PCI Express Non-Transparent Bridge Reset (PENTBRSTN) signal is asserted.
Assertion of the non-transparent bridge fundamental reset (PENTBRSTN) signal when the device is
configured to operate in non-transparent mode and the Propagate External Fundamental Reset (PEFR) bit
is set in the NTBCTL register of the internal or external side of the non-transparent bridge results in a funda-