IDT 89HPES16NT2 User Manual Download Page 99

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IDT Transparent Mode Operation

PES16NT2 User Manual

9 - 13

April 15, 2008

Notes

PA_BAR0 - Base Address Register 0 (0x010)

PA_BAR1 - Base Address Register 1 (0x014)

PA_PBUSN - Primary Bus Number (0x018)

PA_SBUSN - Secondary Bus Number (0x019)

PA_SUBUSN - Subordinate Bus Number (0x01A)

PA_SLTIMER - Secondary Latency Timer (0x01B)

Bit

Field

Name

Type

Default

Value

Description

31:0

BAR

0x0

Base Address Register.

Not applicable.

Bit

Field

Name

Type

Default

Value

Description

31:0

BAR

0x0

Base Address Register.

Not applicable.

Bit

Field

Name

Type

Default

Value

Description

7:0

PBUSN

0x0

Primary Bus Number.

This field is used to record the bus

number of the PCI bus segment to which the primary inter-
face of the bridge is connected.

Bit

Field

Name

Type

Default

Value

Description

7:0

SBUSN

0x0

Secondary Bus Number.

This field is used to record the

bus number of the PCI bus segment to which the second-
ary interface of the bridge is connected.

Bit

Field

Name

Type

Default

Value

Description

7:0

SUBUSN

0x0

Subordinate Bus Number.

The Subordinate Bus Number

register is used to record the bus number of the highest
numbered PCI bus segment which is behind (or subordi-
nate to) the bridge.

Bit

Field

Name

Type

Default

Value

Description

7:0

SLTIMER

0x0

Secondary Latency Timer.

Not applicable.

Summary of Contents for 89HPES16NT2

Page 1: ...6024 Silver Creek Valley Road San Jose California 95138 Telephone 800 345 7015 408 284 8200 FAX 408 284 2775 Printed in U S A 2008 Integrated Device Technology Inc IDT 89HPES16NT2 PCI Express Switch...

Page 2: ...PLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT CONSEQUENTIAL INCIDENTAL INDIRECT PUNITIVE OR SPE...

Page 3: ...he power management capability structure located in the configuration space of each PCI PCI bridge in the PES16NT2 Chapter 6 SMBus Interfaces describes the operation of the 2 SMBus interfaces on the P...

Page 4: ...hexadecimal format is as follows 0xDD where D represents the hexadecimal digit s otherwise it is decimal The compressed notation ABC x y z D refers to ABCxD ABCyD and ABCzD The compressed notation AB...

Page 5: ...h this attribute Reading the value will automatically cause the register bits to be reset to zero Writes cause the register bits to be modified Reserved Reserved The value read from a reserved registe...

Page 6: ...rite Clear RW1C Software can read and write to registers bits with this attribute However writing a value of zero to a bit with this attribute has no effect A RW1C bit can only be set to a value of 1...

Page 7: ...s 1 3 System Identification 1 4 Vendor ID 1 4 Device ID 1 4 Revision ID 1 5 JTAG ID 1 5 Logic Diagram 1 6 Pin Description 1 7 Pin Characteristics 1 10 Clocking Reset and Initialization Introduction 2...

Page 8: ...Static Upstream Port Failover 7 3 Dynamic Upstream Port Failover 7 3 General Purpose I O Introduction 8 1 GPIO Registers 8 1 GPIO Configuration 8 2 GPIO Pin Configured as an Input 8 2 GPIO Pin Config...

Page 9: ...ility Structure 10 38 Switch Control and Status Registers 10 41 Extended Configuration Space Access and INTx Status Registers 10 47 PCI Express Virtual Channel Capability 10 48 Physical Layer Control...

Page 10: ...146 JTAG Boundary Scan Introduction 11 1 Test Access Point 11 1 Signal Definitions 11 1 Boundary Scan Chain 11 3 Test Data Register DR 11 3 Boundary Scan Registers 11 4 Instruction Register IR 11 5 E...

Page 11: ...tion Errors 6 8 Table 6 7 Slave SMBus Address When a Static Address is Selected 6 9 Table 6 8 Slave SMBus Command Code Fields 6 10 Table 6 9 CSR Register Read or Write Operation Byte Sequence 6 11 Tab...

Page 12: ...IDT List of Tables PES16NT2 User Manual vi April 15 2008 Notes Table 11 3 Instructions Supported by PES16NT2 s JTAG Boundary Scan 11 6 Table 11 4 System Controller Device Identification Register 11 7...

Page 13: ...erial EEPROM Read or Write CMD Field Format 6 12 Figure 6 8 CSR Register Read Using SMBus Block Write Read Transactions with PEC Disabled 6 13 Figure 6 9 Serial EEPROM Read Using SMBus Block Write Rea...

Page 14: ...DT List of Figures PES16NT2 User Manual viii April 15 2008 Notes...

Page 15: ...18 9 13 PA_PCICMD PCI Command 0x004 9 9 PA_PCIECAP PCI Express Capability 0x040 9 19 PA_PCIEDCAP PCI Express Device Capabilities 0x044 9 19 PA_PCIEDCTL PCI Express Device Control 0x048 9 20 PA_PCIEDST...

Page 16: ...atus 0x0A8 10 43 PC_HDR Header Type 0x00E 10 24 PC_INTRLINE Interrupt Line 0x03C 10 30 PC_INTRPIN Interrupt PIN 0x03D 10 30 PC_INTSTS Interrupt Status 0x0F4 10 47 PC_IOBASE I O Base 0x01C 10 26 PC_IOB...

Page 17: ...up 0x07C 10 125 PCEE_BARSETUP1 BAR 1 Setup 0x084 10 127 PCEE_BARSETUP2 BAR 2 Setup 0x08C 10 129 PCEE_BARSETUP3 BAR 3 Setup 0x094 10 131 PCEE_BARSETUP4 BAR 4 Setup 0x09C 10 133 PCEE_BARTBASE0 BAR 0 Tra...

Page 18: ...Capability 0x100 10 145 PCEE_PCIELCAP PCI Express Link Capabilities 0x04C 10 119 PCEE_PCIELCTL PCI Express Link Control 0x050 10 119 PCEE_PCIELSTS PCI Express Link Status 0x052 10 120 PCEE_PCISTS PCI...

Page 19: ...on Transparent Bridge Configuration 0x200 10 98 PCIE_NTBCFGC Non Transparent Bridge Configuration Capability 0x074 10 73 PCIE_NTBCOMC Non Transparent Bridge Communications Capability 0x0B4 10 89 PCIE_...

Page 20: ...IDT Register List PES16NT2 User Manual xiv April 15 2008 Notes...

Page 21: ...e board layout with a minimum number of board layers With support for non transparent bridging the PES16NT2 is part of the IDT PCIe System Interconnect Products that target multi host and intelligent...

Page 22: ...and port C as the non transparent downstream port Port C resides on the internal PCI Bus at Device 1 Function 0 Type 1 Configuration Header PCI PCI Transparent Bridge Internal Type 0 Configuration Hea...

Page 23: ...s Supports locked transactions allowing use with legacy software Ability to load device configuration from serial EEPROM Ability to control device via SMBus Non Transparent Port Crosslink support on N...

Page 24: ...e specification Revision 1 1 PCI PM Unused SerDes are disabled Testability and Debug Features Built in SerDes Pseudo Random Bit Stream PRBS generator Ability to read and write any internal register vi...

Page 25: ...d is easily modified during a metal mask change The revision ID shall be incremented with each all layer or metal mask change JTAG ID The JTAG ID is Version Same value as Revision ID See the Revision...

Page 26: ...Bus Interface CCLKUS RSTHALT System Functions JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG VSS SWMODE 3 0 4 2 2 PEATP 0 PEATN 0 PEARP 0 PEARN 0 PEARP 1 PEARN 1 PEARP 7 PEARN 7 PCI Express Switch SerDes...

Page 27: ...ifferential PCI Express receive pairs for port C PECTP 7 0 PECTN 7 0 O PCI Express Port C Serial Data Transmit Differential PCI Express trans mit pairs for port C PEREFCLKP 1 0 PEREFCLKN 1 0 I PCI Exp...

Page 28: ...ed as a general purpose I O pin Alternate function pin name FAILOVERP Alternate function pin type Input Alternate function NTB upstream port failover GPIO 6 I O General Purpose I O This pin can be con...

Page 29: ...ata into or out of the boundary scan logic or JTAG Controller JTAG_TCK is independent of the system clock with a nominal 50 duty cycle JTAG_TDI I JTAG Data Input This is the serial data input to the b...

Page 30: ...ess Termination Power VSS I Ground Function Pin Name Type Buffer I O Type Internal Resistor Notes PCI Express Interface PEALREV I LVTTL Input pull down PEARN 7 0 I CML Serial link PEARP 7 0 I PEATN 7...

Page 31: ...up MSMBSMODE I pull down PENTBRSTN I PERSTN I RSTHALT I pull down SWMODE 3 0 I pull up JTAG JTAG_TCK I LVTTL STI pull up JTAG_TDI I pull up JTAG_TDO O Low Drive JTAG_TMS I STI pull up JTAG_TRST_N I pu...

Page 32: ...IDT PES16NT2 Device Overview PES16NT2 User Manual 1 12 April 15 2008 Notes...

Page 33: ...e clock differential inputs feeds six on chip PLLs Each PLL generates a 2 5 GHz clock which is used by four SerDes lanes and produces a 250 MHz core clock The 250 MHz core clock output from one of the...

Page 34: ...stream must disable Spread Spectrum Clock Figure 2 3 Common Clock on Upstream Non Common Clock on Downstream must disable Spread Spectrum Clock PES16NT2 Port A Port C CCLKDS CCLKUS REFCLK0 REFCLK1 EP...

Page 35: ...t configuration signals in Table 2 2 sampled during the most recent cold reset may be determined by reading the PA_SWSTS register Signal May Be Overridden Description CCLKDS Y Common Clock Downstream...

Page 36: ...e RSTHALT bit in the PA_SWCTL register SWMODE 3 0 N Switch Mode These configuration pins determine the PES16NT2 switch operating mode 0x0 Transparent mode 0x1 Transparent mode with serial EEPROM initi...

Page 37: ...re and remains in a reset state with the Master and Slave SMBuses active This allows software to read and write registers internal to the device before normal device opera tion begins The device exits...

Page 38: ...selected N in NTB mode N N NTB Internal Endpoint All Registers Y N N N N N NTB Internal Endpoint All Registers Except Those of Type Sticky or RWL Y Y2 Y2 Y2 only if port C reset N N NTB External Endpo...

Page 39: ...of a device The reset sequence above guarantees that normal operation will begin within this period as long as the serial EEPROM initialization process completes within 200 ms Under normal circumstanc...

Page 40: ...a hot reset received on a down stream port do not result in a hot reset of the downstream port or any function inside the switch When a globally initiated hot reset occurs all of the logic associated...

Page 41: ...ernal side and external sides of the non transparent bridge Associated with each side of the non transparent bridge are control and status registers NTBCTL and NTBSTS that aid in the handling of hot a...

Page 42: ...lt to GPIO inputs Therefore the downstream port resets are tri stated A system designer should use a pull down on these signals if they are used as reset outputs Internal Side Hot Reset An internal si...

Page 43: ...tion speci fied by the Reset Action RA field in that register is performed This can result in the internal or external side of the non transparent bridge becoming not ready and may be used by the syst...

Page 44: ...IDT Clocking Reset and Initialization Clock Operation PES16NT2 User Manual 2 12 April 15 2008 Notes...

Page 45: ...this field allows the maximum link width of the port to be configured The new link width takes effect the next time link training occurs To force a link width to x4 despite a link partner s ability to...

Page 46: ...RP 5 PExRP 6 PExRP 7 PES16NT2 lane 0 lane 1 lane 2 lane 3 c x4 Port with PExLREV negated PExRP 0 PExRP 1 PExRP 2 PExRP 3 PExRP 4 PExRP 5 PExRP 6 PExRP 7 PES16NT2 lane 3 lane 2 lane 1 lane 0 d x4 Port...

Page 47: ...2 lane 3 lane 2 lane 1 lane 0 b x4 Port with PExLREV asserted PExRP 0 PExRP 1 PExRP 2 PExRP 3 PExRP 4 PExRP 5 PExRP 6 PExRP 7 PES16NT2 lane 0 lane 1 c x2 Port with PExLREV negated PExRP 0 PExRP 1 PExR...

Page 48: ...ion will be retired When a link comes up flow control credits for the configured size of the IFB FIFOs are advertised Slot Power Limit Support The Set_Slot_Power_Limit message is used to convey a slot...

Page 49: ...en the LTSSM is in the L0 L0s L1 or recovery states When the data link layer is down this output is negated An interrupt may be generated by the external or internal NTB endpoints when a change occurs...

Page 50: ...IDT Link Operation PES16NT2 User Manual 3 6 April 15 2008 Notes...

Page 51: ...e switch core is responsible for maintaining flow control information Figure 4 1 PES16NT2 Switch Data Flow and Buffering TLPs are received by a port stack and passed to the switch core Associated with...

Page 52: ...is a timestamp An egress scheduler always selects the TLP in the input buffer that contains the oldest timestamp If that TLP is destined for a different egress port then the egress scheduler makes no...

Page 53: ...des routing using in specification defined transactions as well as those that may be used in vendor defined messages and in future revisions of the PCIe specifications Specifically the PES16NT2 suppor...

Page 54: ...s computed on the received TLP data If an LCRC error is detected at this point the link level retransmission protocol is used to recover from the error by forcing a retransmission by the link partner...

Page 55: ...a TLP is discarded from a posted input buffer the Posted TLP Time out Count PTLPTOC field is incremented in the Switch System Integrity Time Out Drop Count SWSITDCNT register in the port on which the...

Page 56: ...o limited buffering of Unsup ported Request UR completions it is possible for the PES16NT2 to discard UR completions if errors are generated faster than UR completions can be transmitted Even when UR...

Page 57: ...equests Reception of a TLP destined to a disabled downstream port link down or MAE IOAE bit cleared in PA_PCICMD register TLPs destined to a disabled downstream port should be treated as unsupported r...

Page 58: ...t s VGA Enable VGAEN bit is set in its Bridge Control BCTRL register Reception of a TLP destined to a disabled downstream port link down or MAE IOAE bit cleared in PCICMD register or the upstream port...

Page 59: ...entire device When the root port enters a low power state and the PME_TO_Ack messages are received then the entire device is placed into a low power state The PES16NT2 supports the following device po...

Page 60: ..._Off Message There is no TLP or DLLP communications over a link in this state L3 Link is completely unpowered and off Link states are shown in Figure 5 2 From State To State Description Any D0 Uniniti...

Page 61: ...s Entry Timer L0SET field in the PCI Power Management Proprietary Control PMPC register controls the amount of time L0s entry conditions must be met before the hardware transitions the link to the L0s...

Page 62: ...IDT Power Management PES16NT2 User Manual 5 4 April 15 2008 Notes...

Page 63: ...onfiguration Examples In the unified configuration shown in Figure 6 1 a the master and slave SMBuses are tied together and the PES16NT2 acts both as an SMBus master as well as an SMBus slave on this...

Page 64: ...ring a master SMBus transaction The setting of this bit may indicate the following that the addressed device does not exist on the SMBus i e addressing error data is unavailable or the device is busy...

Page 65: ...the checksum always passes 19 18 SSMBMODE RW 0x0 Slave SMBus Mode The slave SMBus contains internal glitch counters on the SSMBCLK and SSMBDAT signals that wait approximately 1 S before sampling or dr...

Page 66: ...DDR 4 1 signals as shown in Table 6 3 Device Initialization from a Serial EEPROM During initialization from the optional serial EEPROM the master SMBus interface reads configuration blocks from the se...

Page 67: ...iguration block types that may be stored in the serial EEPROM The first type is a single double word initialization sequence A double word initialization sequence occupies six byes in the serial EEPRO...

Page 68: ...system address to be initialized The next field is the TYPE field that indicates the type of the configuration block For sequen tial double word initialization sequences this value is always 0x1 The...

Page 69: ...ed over the configuration bytes stored in the serial EEPROM including the entire contents of the configuration done sequence with the checksum field initialized to zero 1 The 1 s complement of this su...

Page 70: ...d results SMBus errors may occur when accessing the serial EEPROM If an error occurs it is reported in the port A SMBus Status PA_SMBUSSTS register Software should check for errors before and after ea...

Page 71: ...ailed description of these transactions Byte and Word Write Read Block Write Read Initiation of any SMBus transaction other than those listed above to the slave SMBus interface produces undefined resu...

Page 72: ...icator Setting both START and END signifies a single transaction sequence 0 Current transaction is not the last read or write sequence 1 Current transaction is the last read or write sequence 1 START...

Page 73: ...leword CSR system address of register to access 4 ADDRU Address Upper Upper 6 bits of the doubleword CSR system address of register to access Bits 6 and 7 in the byte must be zero and are ignored by t...

Page 74: ...E Command Code Slave Command Code field described in Table 6 8 1 BYTCNT Byte Count The byte count field is only transmitted for block type SMBus transactions SMBus word and byte accesses do not contai...

Page 75: ...NAERR bit in the PA_SMBUSSTS register The setting of this bit may indicate the following that the addressed device does not exist on the SMBus i e addressing error data is unavailable or the device is...

Page 76: ...Slave SMBus Address Rd ADDRU A BYTCNT 5 A EEADDR CMD status A A A N DATA ADDRU A P ADDRL A S PES16NT2 Slave SMBus Address Wr A N CCODE START END P PES16NT2 not ready with data S PES16NT2 Slave SMBus...

Page 77: ...RT Word S PES16NT2 Slave SMBus Address Rd DATALM DATALL A N P P S PES16NT2 Slave SMBus Address Wr A A ADDRU A CCODE END Byte P A S PES16NT2 Slave SMBus Address Wr A CCODE Byte A P A S PES16NT2 Slave S...

Page 78: ...IDT SMBus Interfaces PES16NT2 User Manual 6 16 April 15 2008 Notes...

Page 79: ...m port failover architecture is shown in Figure 7 2 The two main compo nents of this device are switch logic and a SerDes switch The PES16NT2 switch logic implements a two port non transparent switch...

Page 80: ...it results in a complete loss of system state Dynamic NTB upstream port failover allows the operating mode of the PES16NT2 to be modified from normal to failover or failover to normal while the syste...

Page 81: ...owing steps Assert the PCIe fundamental reset signal PERSTN Modify the switch mode SWMODE signals to the selected failover mode i e normal mode or failover mode Negate the PCIe fundamental reset signa...

Page 82: ...itions from a one to a zero When non zero the COUNT field in the USPFTIMER is decremented once per microsecond 1 S This provides a maximum watchdog timer interval of over one hour Decrementing of the...

Page 83: ...IDT NTB Upstream Port Failover PES16NT2 User Manual 7 5 April 15 2008 Notes...

Page 84: ...IDT NTB Upstream Port Failover PES16NT2 User Manual 7 6 April 15 2008 Notes...

Page 85: ...e alternate function as defined in Table 8 2 When a bit is cleared to a zero the correspond ing GPIO pin operates as a general purpose I O pin 15 8 GPIOCFG RW 0x0 GPIO Configuration Each bit in this f...

Page 86: ...n this field corresponds to the value of the pin irre spective of whether the pin is configured as a GPIO input GPIO output or alternate function GPIO Pin Configured as an Output When configured as an...

Page 87: ...ed with each port is a 4 KB configuration space and a Type 1 configuration header The organi zation of these configuration spaces is described in section section Port Configuration Space Organization...

Page 88: ...This section describes error detection performed by an ingress or egress stack when the switch is configured to operate in transparent mode Table 9 1 lists error checks performed by the physical layer...

Page 89: ...d by AckNak_Seq does not correspond to an unacknowledged TLP or to the value in ACKD_SEQ 3 5 2 1 Uncorrectable error processing 1 A bad DLLP is a DLP with a bad LCRC Error Condition PCIe Base 1 0a Spe...

Page 90: ...ENGTH 1 doubleword TC 0 ATTR 0 The actual packet length is correct 5 doublewords when CRC is present 4 doublewords otherwise Memory read request 32 and 64 bit address mode The packet length is correct...

Page 91: ...ses to any particular entity always complete in order Port Configuration Space Organization The organization of ports A and C configuration space is shown in Figure 9 2 While both ports share the same...

Page 92: ...press Capability Structure 0xFFF 0x100 0x070 0x040 0x000 PCI Configuration Space 64 DWords PCI Express Extended Configuration Space 960 DWords Virtual Channel Capability Structure PCI Power Management...

Page 93: ...Line Size 0x00C on page 9 12 0x00D Byte PA_PLTIMER PA_PLTIMER Primary Latency Timer 0x00D on page 9 12 0x00E Byte PA_HDR PA_HDR Header Type 0x00E on page 9 12 0x00F Byte PA_BIST PA_BIST Built in Self...

Page 94: ...70 DWord PA_PMCAP PA_PMCAP PCI Power Management Capabilities 0x070 on page 9 26 0x074 DWord PA_PMCSR PA_PMCSR PCI Power Management Control and Status 0x074 on page 9 27 0x078 DWord PA_PMPC PA_PMPC PCI...

Page 95: ...fication This field contains the 16 bit ven dor ID value assigned to IDT See section Vendor ID on page 1 4 Bit Field Field Name Type Default Value Description 15 0 DID RO Device Identification This fi...

Page 96: ...gister is never set 0x0 disable Disable Master Parity Error bit reporting 0x1 enable Enable Master Parity Error bit reporting 7 ADSTEP RO 0x0 Address Data Stepping Not applicable 8 SERRE RW 0x0 SERR E...

Page 97: ...Not applicable since a target abort is never signalled 12 RTAS RO 0x0 Received Target Abort Not applicable 13 RMAS RO 0x0 Received Master Abort Not applicable 14 SSE RW1C 0x0 Signalled System Error Th...

Page 98: ...06 Base Class Code This value indicates that the device is a bridge Bit Field Field Name Type Default Value Description 7 0 CLS RW 0x00 Cache Line Size This field has no effect on the bridge s functio...

Page 99: ...e Description 7 0 PBUSN RW 0x0 Primary Bus Number This field is used to record the bus number of the PCI bus segment to which the primary inter face of the bridge is connected Bit Field Field Name Typ...

Page 100: ...sing This bit always reflects the value of the IOCAP field in the IOBASE register 3 1 Reserved RO 0x0 Reserved field 7 4 IOLIMIT RW 0x0 I O Limit The IOBASE and IOLIMIT registers are used to control t...

Page 101: ...15 4 MBASE RW 0xFFF Memory Address Base The MBASE and MLIMIT regis ters are used to control the forwarding of non prefetchable transactions between the primary and secondary interfaces of the bridge T...

Page 102: ...the PMBASE register 3 1 Reserved RO 0x0 Reserved field 15 4 PMLIMIT RW 0x0 Prefetchable Memory Address Limit The PMBASE PMBASEU PMLIMIT and PMLIMITU registers are used to control the forwarding of pre...

Page 103: ...he upper 16 bits of IOLIMIT When the IOCAP field in the IOBASE register is cleared this field becomes read only with a value of zero Bit Field Field Name Type Default Value Description 7 0 CAPPTR RO 0...

Page 104: ...warding of ERR_COR ERR_NONFATAL ERR_FATAL from the sec ondary interface of the bridge to the primary interface Note that error reporting must be enabled in the Command register or PCI Express Capabili...

Page 105: ...This field indicates the maximum payload size that the device can support for TLPs The default value corresponds to 2048 bytes 4 3 PFS RO 0x0 Phantom Functions Supported This field indicates the supp...

Page 106: ...the Slot Power Limit Scale field This value is set by the Set_Slot_Power_Limit Message 27 26 CSPLS RO 0x0 Captured Slot Power Limit Scale Upstream Port A only hardwired to zero in downstream ports Th...

Page 107: ...ith the No Snoop bit unmodified Therefore this field has no functional effect on the behavior of the transparent bridge 14 12 MRRS RO 0x0 Maximum Read Request Size The transparent bridge does not gene...

Page 108: ...to a invalid or reserved value results in x1 being used 1 x1 x1 link width 2 x2 x2 link width 4 x4 x4 link width 8 x8 x8 link width others reserved 11 10 ASPMS RO 0x3 Active State Power Management ASP...

Page 109: ...ayer LTSSM to the Recovery state This field always returns zero when read For compliance with the PCIe specification this bit has no effect on the upstream port when the REGUNLOCK bit is cleared in th...

Page 110: ...t supported 6 HPC RO 0x0 Hot Plug Capable Hot plug is not supported 14 7 SPLV RWL 0x0 Slot Power Limit Value In combination with the Slot Power Limit Scale this field specifies the upper limit on powe...

Page 111: ...pported 4 CCIE RO 0x0 Command Complete Interrupt Enable Hot plug is not supported 5 HPIE RO 0x0 Hot Plug Interrupt Enable Hot plug is not supported 7 6 AIC RO 0x3 Attention Indicator Control Hot plug...

Page 112: ...version two of the specification 19 PMECLK RO 0x0 PME Clock Does not apply to PCI Express 20 Reserved RO 0x0 Reserved field 21 DEVSP RWL 0x0 Device Specific Initialization The value of zero indicates...

Page 113: ...ect The optional data register is not implemented 14 13 DSCALE RO 0x0 Data Scale The optional data register is not implemented 15 PMES RW1C 0x0 Sticky for port C RO 0x0 for port A PME Status This bit...

Page 114: ...en the transmitter port enters L0s The timer value is specified in the number 4ns clock cycles The default value corresponds to the PCI Express value of 7 S 30 28 Reserved RO 0x0 Reserved field 31 MCS...

Page 115: ...10 L1comply_0 6 d11 L1comply_1 6 d12 L1comply_2 6 d13 L1accept_0 6 d14 L1accept_1 6 d15 L1accept_2 6 d16 L1reject_0 6 d17 L1timed_0 6 d18 L1timed_1 6 d19 L1timed_2 6 d20 L1timed_3 6 d21 L1timed_nak 6...

Page 116: ...the fundamental reset 6 MSMBSMODE RO HWINIT Master SMBus Slow Mode This bit reflects the value of the MSMBSMODE signal sampled during the fundamental reset 7 PALREV RO HWINIT PCI Express Port A Lane R...

Page 117: ...e In this state registers in the device may be initialized by the slave SMBus interface When this bit is cleared normal opera tion ensues Setting or clearing this bit has no effect following a reset o...

Page 118: ...perate in non transparent mode 0x0 extreset external reset In this mode the PECRSTN pin is asserted when an external hot or fundamental reset is detected 0x1 intreset internal reset In this mode the P...

Page 119: ...PROM initialization completes or when an error is detected 25 NAERR RW1C 0x0 No Acknowledge Error This bit is set if an unexpected NACK is observed during a master SMBus transaction The setting of thi...

Page 120: ...nters on the SSMBCLK and SSMBDAT signals that wait approximately 1 S before sampling or driving these signals This field allows the glitch counter time to be reduced or entirely removed In some system...

Page 121: ...pecified in the ADDR field When a write operation is selected the value written to this field is the value written to the serial EEPROM When a read operation is selected the value written to this fiel...

Page 122: ...RO 0x0 INTC Aggregated State Aggregated port state for INTC 0x0 negated INTC negated 0x1 asserted INTC asserted 3 INTD RO 0x0 INTD Aggregated State Aggregated port state for INTD 0x0 negated INTD nega...

Page 123: ...gister SMBus reads of this field return a value of zero and SMBus writes have no effect Bit Field Field Name Type Default Value Description 15 0 CAPID RO 0x2 Capability ID The value of 0x2 indicates a...

Page 124: ...0x0 Reserved field 14 APS RO 0x0 Advanced Packet Switching Not supported 15 RJST RO 0x0 Reject Snoop Transactions Not supported for switch ports 22 16 MAXTS RO 0x0 Maximum Time Slots Since this VC doe...

Page 125: ...s to one of the asserted bits in the Port Arbitration Capability field of the VC resource 23 20 Reserved RO 0x0 Reserved field 26 24 VCID RO 0x0 VC ID This field assigns a VC ID to the VC resource Sin...

Page 126: ...iod 11 10 PHASE5 RW 0x0 Phase 5 This field contains the port ID for the correspond ing port arbitration period 13 12 PHASE6 RW 0x0 Phase 6 This field contains the port ID for the correspond ing port a...

Page 127: ...for the corre sponding port arbitration period 13 12 PHASE22 RW 0x0 Phase 22 This field contains the port ID for the corre sponding port arbitration period 15 14 PHASE23 RW 0x0 Phase 23 This field co...

Page 128: ...the nominal drive current selected by the TXNDC field multiplied by the scale factor selected in this field 0x0 sf100 scale factor of 1 00 0x1 sf105 scale factor of 1 05 0x2 sf110 scale factor of 1 1...

Page 129: ...on value of nominal 10 0x3 m15 termination value of nominal 15 14 HIVMODE RW 0x0 High Voltage Mode This field selects the SerDes Vdd VddA supply voltage 0x0 low 1 0V supply 0x1 high 1 2V supply 16 15...

Page 130: ...IDT Transparent Mode Operation PES16NT2 User Manual 9 44 April 15 2008 Notes...

Page 131: ...associated with port C are two endpoints interconnected by non transparent bridge function ality When viewed externally port C appears as an end point device When viewed internally the non transparen...

Page 132: ...tch integrity control and status registers in the port C configuration space are still associated with the port C PCI PCI bridge The connection between the port C PCI PCI bridge and the internal endpo...

Page 133: ...s received by an internal or external non transparent endpoint that does not correspond to a message that should be processed by an endpoint then the message is silently discarded Address Routing Addr...

Page 134: ...s or any combination of the two Each BAR has a corresponding setup register translated base register and translated limit register in the Non Transparent Bridge Configuration Capability structure asso...

Page 135: ...on number would be six If a posted address routed transaction is received that matches a BAR but whose requester ID is not in the mapping table then the Forward Mapping Table Miss FMTMISS bit is set i...

Page 136: ...ping table entry containing the bus device and function numbers of the original requestor The mapping table entry address formed from the device and function numbers is used to index into the mapping...

Page 137: ...s are read only When an OUTMSG register is written the corresponding INMSG register on the opposite side of the NTB takes on the value written and the corresponding Inbound Message INMSGx bit is set i...

Page 138: ...dpoint interrupts and MSIs are sent out on the link associated with the non transparent bridge i e port C link Each interrupt source has an associated bit in the Interrupt Status INTSTS register Assoc...

Page 139: ...that are Message Signaled Interrupts MSIs and Message requests except where specifically permitted Since MSIs cannot be distinguished from memory write transactions by the switch the relaxed ordering...

Page 140: ...four or less outstanding configuration transactions to an NTB configuration space Exceeding this number of outstanding transactions may result in completions being dropped In some systems it may desir...

Page 141: ...sm referred to as punch through is provided to facilitate systems in which there does not exist a root on the external side of the NTB The external endpoint is unable to generate configura tion transa...

Page 142: ...s generated to the root on which the packet was received if non fatal error reporting is enabled in the corresponding device control register i e Non Fatal Error Reporting Enable NTEREN bit set in the...

Page 143: ...Q and this is not a duplicate TLP 3 5 3 1 Correctable error processing Bad DLLP1 1 A bad DLLP is a DLP with a bad LCRC 3 5 2 1 Correctable error processing Replay time out 3 5 2 1 Correctable error pr...

Page 144: ...en a TLP is received by the switch TLP Type Error Check All LENGTH Max_Payload_Size i e MPS field in PCIEDCTL register I O read request LENGTH 1 doubleword TC 0 ATTR 0 The actual packet length is corr...

Page 145: ...ddress mode Number of doublewords received equals LENGTH 4 when ECRC is present Number of doublewords received equals LENGTH 3 when a packet does not contain ECRC 64 bit address mode Number of doublew...

Page 146: ...ry Access Enable MAE bit should be set in the PC_PCICMD register to enable the port C PCI PCI bridge to forward memory transactions The Memory Access Enable MAE bit should be set in the PCIE_PCICMD re...

Page 147: ...transparent bridge to forward I O transactions into the switch The Bus Master Enable BME bit should be set in the PCIE_PCICMD register to enable the internal endpoint of the non transparent bridge to...

Page 148: ...10 6 Figure 10 6 Port C Configuration Space Organization in Non Transparent Mode Type 1 Configuration Header PCI Express Capability Structure 0x100 0x070 0x040 0x000 PCI Configuration Space 64 DWords...

Page 149: ...che Line Size 0x00C on page 10 24 0x00D Byte PC_PLTIMER PC_PLTIMER Primary Latency Timer 0x00D on page 10 24 0x00E Byte PC_HDR PC_HDR Header Type 0x00E on page 10 24 0x00F Byte PC_BIST PC_BIST Built i...

Page 150: ...0 36 0x054 DWord PC_PCIESCAP PC_PCIESCAP Port C NTB Mode PCI Express Slot Capabilities 0x054 on page 10 36 0x058 Word PC_PCIESCTL PC_PCIESCTL Port C NTB Mode PCI Express Slot Control 0x058 on page 10...

Page 151: ...ld Field Name Type Default Value Description 15 0 DID RO Device Identification This field contains the 16 bit device ID assigned by IDT to this transparent bridge See section section Device ID on page...

Page 152: ...egister is never set 0x0 disable Disable Master Parity Error bit reporting 0x1 enable Enable Master Parity Error bit reporting 7 ADSTEP RO 0x0 Address Data Stepping Not applicable 8 SERRE RW 0x0 SERR...

Page 153: ...t Not applicable since a target abort is never signalled 12 RTAS RO 0x0 Received Target Abort Not applicable 13 RMAS RO 0x0 Received Master Abort Not applicable 14 SSE RW1C 0x0 Signalled System Error...

Page 154: ...0x06 Base Class Code This value indicates that the device is a bridge Bit Field Field Name Type Default Value Description 7 0 CLS RW 0x00 Cache Line Size This field has no effect on the bridge s func...

Page 155: ...lue Description 7 0 PBUSN RW 0x0 Primary Bus Number This field is used to record the bus number of the PCI bus segment to which the primary inter face of the bridge is connected Bit Field Field Name T...

Page 156: ...ressing This bit always reflects the value of the IOCAP field in the IOBASE register 3 1 Reserved RO 0x0 Reserved field 7 4 IOLIMIT RW 0x0 I O Limit The IOBASE and IOLIMIT registers are used to contro...

Page 157: ...e section Data Integrity on page 4 4 Bit Field Field Name Type Default Value Description 3 0 Reserved RO 0x0 Reserved field 15 4 MBASE RW 0xFFF Memory Address Base The MBASE and MLIMIT regis ters are...

Page 158: ...ry interface of the bridge PMBASEU specifies the remaining bits Bit Field Field Name Type Default Value Description 0 PMCAP RO 0x1 Prefetchable Memory Capability Indicates if the bridge supports 32 bi...

Page 159: ...0 IOBASEU RW 0xFFFF I O Address Base Upper This field specifies the upper 16 bits of IOBASE When the IOCAP field in the IOBASE register is cleared this field becomes read only with a value of zero Bi...

Page 160: ...the secondary inter face 0x0 ignore Ignore poisoned TLPs i e parity errors on the secondary interface 0x1 report Enable poisoned TLP i e parity error detection and reporting on the secondary interfac...

Page 161: ...ted This bit is set when the PCI Express link associated with this Port is connected to a slot 29 25 IMN RO 0x0 Interrupt Message Number The function is allocated only one downstream ports MSI or none...

Page 162: ...icator is implemented on the card module This bit should not be set on downstream ports 25 18 CSPLV RO 0x0 Captured Slot Power Limit Value Upstream Port A only hardwired to zero in downstream ports Ca...

Page 163: ...not support phantom function numbers Therefore this field is hard wired to zero 10 AUXPMEN RO 0x0 Auxiliary Power PM Enable The device does not imple ment this capability 11 ENS RO 0x0 Enable No Snoop...

Page 164: ...eld Name Type Default Value Description 3 0 MAXLNKSPD RO 0x1 Maximum Link Speed This field is hardwired to 0x1 to indicate 2 5 Gbps 9 4 MAXLNK WDTH RWL 0x8 Maximum Link Width This field indicates the...

Page 165: ...ault value 0x0 disabled disabled 0x1 l0s L0s enable entry 0x2 l1 L1 enable entry 0x3 l0sl1 L0s and L1 enable entry 2 Reserved RO 0x0 Reserved field 3 RCB RO 0x0 Read Completion Boundary This field is...

Page 166: ...d Bit Field Field Name Type Default Value Description 0 ABP RO 0x0 Attention Button Present Hot plug is not supported 1 PCP RO 0x0 Power Control Present Hot plug is not supported 2 MRLP RO 0x0 MRL Sen...

Page 167: ...Attention Indicator Control Hot plug is not supported 9 8 PIC RO 0x0 Power Indicator Control Hot plug is not supported 10 PCC RO 0x0 Power Controller Control Hot plug is not supported 11 EIC RO 0x0 E...

Page 168: ...field indicates that the PES16NT2 does not support D1 26 D2 RO 0x0 D2 Support This field indicates that the PES16NT2 does not support D2 31 27 PME RO 0b11001 PME Support This field indicates the powe...

Page 169: ...0 L1ET RW 0x3E8 L1 Entry Timer This field specifies the L1 entry timer value for the related port transmitter If all L1 entry condi tions are met for the specified amount of time then the transmitter...

Page 170: ...6 d10 L1comply_0 6 d11 L1comply_1 6 d12 L1comply_2 6 d13 L1accept_0 6 d14 L1accept_1 6 d15 L1accept_2 6 d16 L1reject_0 6 d17 L1timed_0 6 d18 L1timed_1 6 d19 L1timed_2 6 d20 L1timed_3 6 d21 L1timed_nak...

Page 171: ...g the fundamental reset 6 MSMBSMODE RO HWINIT Master SMBus Slow Mode This bit reflects the value of the MSMBSMODE signal sampled during the fundamental reset 7 PALREV RO HWINIT PCI Express Port A Lane...

Page 172: ...ate In this state registers in the device may be initialized by the slave SMBus interface When this bit is cleared normal opera tion ensues Setting or clearing this bit has no effect following a reset...

Page 173: ...o operate in non transparent mode 0x0 extreset external reset In this mode the PECRSTN pin is asserted when an external hot or fundamental reset is detected 0x1 intreset internal reset In this mode th...

Page 174: ...ode in which serial EEPROM initialization occurs during a fundamental reset this bit is set when serial EEPROM initialization completes or when an error is detected 25 NAERR RW1C 0x0 No Acknowledge Er...

Page 175: ...onfigured to operate in fast mode i e 400 KHz 16 MSMBIOM RW 0x0 Master SMBus Ignore Other Masters When this bit is set the master SMBus proceeds with transactions regard less of whether it won or lost...

Page 176: ...sed Bit Field Field Name Type Default Value Description 15 0 ADDR RW 0x0 EEPROM Address This field contains the byte address in the Serial EEPROM to be read or written 23 16 DATA RW 0x0 EEPROM Data A...

Page 177: ...TC RO 0x0 INTC Aggregated State Aggregated port state for INTC 0x0 negated INTC negated 0x1 asserted INTC asserted 3 INTD RO 0x0 INTD Aggregated State Aggregated port state for INTD 0x0 negated INTD n...

Page 178: ...register SMBus reads of this field return a value of zero and SMBus writes have no effect Bit Field Field Name Type Default Value Description 15 0 CAPID RO 0x2 Capability ID The value of 0x2 indicates...

Page 179: ...RO 0x0 Reserved field 14 APS RO 0x0 Advanced Packet Switching Not supported 15 RJST RO 0x0 Reject Snoop Transactions Not supported for switch ports 22 16 MAXTS RO 0x0 Maximum Time Slots Since this VC...

Page 180: ...onds to one of the asserted bits in the Port Arbitration Capability field of the VC resource 23 20 Reserved RO 0x0 Reserved field 26 24 VCID RO 0x0 VC ID This field assigns a VC ID to the VC resource...

Page 181: ...eriod 11 10 PHASE5 RW 0x0 Phase 5 This field contains the port ID for the correspond ing port arbitration period 13 12 PHASE6 RW 0x0 Phase 6 This field contains the port ID for the correspond ing port...

Page 182: ...ID for the corre sponding port arbitration period 13 12 PHASE22 RW 0x0 Phase 22 This field contains the port ID for the corre sponding port arbitration period 15 14 PHASE23 RW 0x0 Phase 23 This field...

Page 183: ...to the nominal drive current selected by the TXNDC field multiplied by the scale factor selected in this field 0x0 sf100 scale factor of 1 00 0x1 sf105 scale factor of 1 05 0x2 sf110 scale factor of...

Page 184: ...tion value of nominal 10 0x3 m15 termination value of nominal 15 14 HIVMODE RW 0x0 High Voltage Mode This field selects the SerDes Vdd VddA supply voltage 0x0 low 1 0V supply 0x1 high 1 2V supply 16 1...

Page 185: ...tion Capability Structure Non Transparent Bridge Communications Capability Structure PCIe Extended Cap Hdr 0xFFF 0x800 0x100 0x0B4 0x074 0x064 0x040 0x000 PCI Non Transparent Bridge Configuration Wind...

Page 186: ...00C on page 10 62 0x00D Byte PCIE_MLTIMER PCIE_MLTIMER Master Latency Timer 0x00D on page 10 62 0x00E Byte PCIE_HDR PCIE_HDR Header Type 0x00E on page 10 62 0x00F Byte PCIE_BIST PCIE_BIST Built on Sel...

Page 187: ...079 on page 10 75 0x07A Word PCIE_NTBEPID PCIE_NTBEPID Non Transparent Bridge Endpoint Identifica tion 0x07A on page 10 76 0x07C DWord PCIE_BARSETUP0 PCIE_BARSETUP0 BAR 0 Setup 0x07C on page 10 77 0x0...

Page 188: ...9 0x0D8 DWord PCIE_SCRATCHPAD0 PCIE_SCRATCHPAD 0 1 Scratchpad 0 1 0x0D8 ODC on page 10 90 0x0DC DWord PCIE_SCRATCHPAD1 PCIE_SCRATCHPAD 0 1 Scratchpad 0 1 0x0D8 ODC on page 10 90 0x0E0 DWord PCIE_INDBE...

Page 189: ...3 Translated Limit Address 0x224 on page 10 103 0x400 through 0xFFF Reserved field Bit Field Field Name Type Default Value Description 15 0 VID RO 0x111D Vendor Identification This field contains the...

Page 190: ...his bit is set and the non transparent bridge receives a poisoned completion or gen erates a poisoned write If this bit is set then the Master Data Parity Error bit in the PCI Status register is never...

Page 191: ...or completion received 10 9 DEVT RO 0x0 DEVSEL TIming Not applicable 11 STAS RO 0x0 Signalled Target Abort Not applicable 12 RTAS RW1C 0x0 Received Target Abort This bit is set when the non trans par...

Page 192: ...escription 7 0 INTF RO 0x00 Interface No standard interface defined 15 8 SUB RO 0x80 Sub Class Code This value indicates that the device is classified as other 23 16 BASE RO 0x06 Base Class Code This...

Page 193: ...x0 addr32 32 bit addressing Located in lower 4 GB address space 0x1 reserved reserved 0x2 addr64 64 bit addressing 0x3 reserved reserved 3 PREF RO Prefetchable If the MEMSI field selects memory this f...

Page 194: ...t 0x0 addr32 32 bit addressing Located in lower 4 GB address space 0x1 reserved reserved 0x1 reserved reserved 0x3 reserved reserved 3 PREF RO Prefetchable If the MEMSI field selects memory this field...

Page 195: ...always zero The value of this field is determined by the PREF field in the BARSETUP2 register 0x0 nonprefetch non prefetchable 0x1 prefetch prefetchable 31 4 BADDR RW 0x0 Base Address This field speci...

Page 196: ...by the MEMSI field in the BARSETUP3 register 0x0 nonprefetch non prefetchable 0x1 prefetch prefetchable 31 4 BADDR RW 0x0 Base Address This field specifies the address bits to be used by the non tran...

Page 197: ...identifies the subsystem Bit Field Field Name Type Default Value Description 7 0 CAPPTR RO 0x40 Capabilities Pointer This field specifies a pointer to the head of the capabilities structure Bit Field...

Page 198: ...lue contained in Serial EEPROM may override this default value 24 SLOT RWL 0x0 Slot Implemented This bit is set when the PCI Express link associated with this Port is connected to a slot 29 25 IMN RO...

Page 199: ...ride this default value 14 PIP RO 0x0 Power Indicator Present When set this bit indicates that a Power Indicator is implemented on the card module The value contained in Serial EEPROM may override thi...

Page 200: ...ment this capability 11 ENS RW 0x0 Enable No Snoop The non transparent bridge does not generate transactions with the No Snoop bit set and passes transactions through the bridge with the No Snoop bit...

Page 201: ...red to 2 5 Gbps 9 4 MAXLNKWDTH RO 0x8 Maximum Link Width This field is hardwired to 0x8 11 10 ASPMS RO 0x01 Active State Power Management This field is hardwired to indicate L0s entry supported Howeve...

Page 202: ...t applicable for endpoints 12 SCLK RO 0x0 Slot Clock Configuration Not applicable for virtual links 15 13 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 7 0 CAPID R...

Page 203: ...mory write transaction If the contents of this field are non zero then 64 bit address is used in the MSI memory write transaction If the contents of this field are zero then the 32 bit address specifi...

Page 204: ...hen the opposite side is set to not ready all configuration transactions received on the opposite side of the non transparent bridge are responded to with a configuration request retry status completi...

Page 205: ...bit is set in this register and a fundament or hot reset is detected on the opposite side of the non transparent bridge This field is only relevant for the internal side of the non transparent bridge...

Page 206: ...ion is received by the opposite side of the non transparent bridge that does match the bus device function of an entry in the mapping table 5 MTAERR RW1C 0x01 Mapping Table Access Error This bit is se...

Page 207: ...0x1 io I O space 2 1 TYPE RW 0x01 Address Select This field determines the value reported in the TYPE field of the corresponding BAR and selects the address space decoding used when memory space is s...

Page 208: ...the SIZE field to a value less than four results in all bits in the corresponding BAR BADDR field to take on a read only zero value that effectively disables the BAR The smallest memory size that may...

Page 209: ...t by external fundamental reset or internal external hot reset Bit Field Field Name Type Default Value Description 0 MEMSI RW 0x01 MEMSI Select This field determines the MEMSI type returned in the MEM...

Page 210: ...d Corresponding bits less than the SIZE field and greater than or equal to four always return a value of zero when read and cannot be modified Setting the SIZE field to a value less than four results...

Page 211: ...nding BAR 0x0 memory memory space 0x1 io I O space 2 1 TYPE RW 0x01 Address Select This field determines the value reported in the TYPE field of the corresponding BAR and selects the address space dec...

Page 212: ...the SIZE field to a value less than four results in all bits in the corresponding BAR BADDR field to take on a read only zero value that effectively disables the BAR The smallest memory size that may...

Page 213: ...t by external fundamental reset or internal external hot reset Bit Field Field Name Type Default Value Description 0 MEMSI RW 0x01 MEMSI Select This field determines the MEMSI type returned in the MEM...

Page 214: ...the BAR BADDR field that corre spond to PCI Express address bits greater than or equal to the SIZE field to be modified Corresponding bits less than the SIZE field and greater than or equal to four a...

Page 215: ...corresponding BAR 32 bit addressing is always selected 3 PREF RO 0x0 Prefetchable Select This field determines the value reported in the PREF field of the corresponding BAR Non prefetchable space is a...

Page 216: ...med when the PTCDATA regis ter is written 0x0 read configuration read 0x1 write configuration write 1 Not reset by external fundamental reset or internal external hot reset Bit Field Field Name Type D...

Page 217: ...ion Status This field contains the completion status of the last punch through configuration transaction and is valid only when the DONE bit in this register is set 0x0 sc successful completion 0x1 ur...

Page 218: ...g table entry pointed to by the ADDR field in the MTADDR register Writing this field updates the mapping table entry pointed to by the ADDR field Only DWord accesses are supported to this register Non...

Page 219: ...T proprietary PCI PCI X or PCI Express capability The value of 0x2 identifies this as a non transparent bridge communications capability structure Bit Field Field Name Type Default Value Description 3...

Page 220: ...located in PCI configuration space on the opposite side of the of the non transparent bridge Bit Field Field Name Type Default Value Description 31 0 OUTDBELL RW 0x0 Outbound Doorbell Each bit in this...

Page 221: ...t Control 0 INTCTL0 register 6 OSPSTATEM RW1C 0x0 Opposite Side Power State Modification This bit is set whenever a modification is made to the PSTATE field in the PMCSR register on the opposite side...

Page 222: ...e INTB assertion and negation mes sages 0x4 int_c generate INTC assertion and negation mes sages 0x5 int_d generate INTD assertion and negation mes sages 0x6 though 0x8 reserved reserved 5 3 INMSG1 RW...

Page 223: ...n and negation mes sages 0x5 int_d generate INTD assertion and negation mes sages 0x6 though 0x8 reserved reserved 11 9 INMSG3 RW 0x0 Inbound Message 3 Configuration This field encodes the action take...

Page 224: ...d negation mes sages 0x5 int_d generate INTD assertion and negation mes sages 0x6 though 0x7 reserved reserved 17 15 OSRD RW 0x0 Opposite Side Reset Detected Configuration This field encodes the actio...

Page 225: ...TA assertion and negation mes sages 0x3 int_b generate INTB assertion and negation mes sages 0x4 int_c generate INTC assertion and negation mes sages 0x5 int_d generate INTD assertion and negation mes...

Page 226: ...mine the current power state and to set a new power state 0x0 d0 D0 state 0x1 d1 D1 state not supported by the PES16NT2 and reserved 0x2 d2 D2 state not supported by the PES16NT2 and reserved 0x3 d3 D...

Page 227: ...guration Data A read from this field will return the configuration space register value pointed to by the ECF GADDR register A write to this field will update the con tents of the configuration space...

Page 228: ...dless of the value of this field an MSI is only sent when the Enable EN bit is set in the MSICAP register Similarly and INTx message is only sent if not disabled by the INTXD bit in the PCICMD registe...

Page 229: ...on and negation mes sages 0x5 int_d generate INTD assertion and negation mes sages 0x6 though 0x8 reserved reserved 8 6 PBLINKUP RW 0x0 Port B Link Up Configuration This field encodes the action taken...

Page 230: ...on and negation mes sages 0x5 int_d generate INTD assertion and negation mes sages 0x6 though 0x8 reserved reserved 14 12 PCLINKUP RW 0x0 Port C Link Up Configuration This field encodes the action tak...

Page 231: ...PCICMD register The action i e this field should not be modified while the corresponding bit is set Modifying the action when the cor responding bit is set produces undefined results 0x0 disabled int...

Page 232: ...ttribute 2 FNS RW 0x0 Sticky Force No Snoop When this bit is set all TLPs in which the no snoop attribute is applicable are modified as dic tated by the No Snoop Modification NSM field in this reg ist...

Page 233: ...address for transactions that map through BAR1 of the non transparent bridge A translation fails the limit test if the address is greater than the value specified in this field Bit Field Field Name T...

Page 234: ...ification 0x008 on page 10 110 0x009 3 Bytes PCEE_CCODE PCEE_CCODE Class Code 0x009 on page 10 110 0x00C Byte PCEE_CLS PCEE_CLS Cache Line Size 0x00C on page 10 110 0x00D Byte PCEE_MLTIMER PCEE_MLTIME...

Page 235: ...10 121 0x074 DWord PCEE_NTBCFGC PCEE_NTBCFGC Non Transparent Bridge Configuration Capability 0x074 on page 10 121 0x078 Byte PCEE_NTBCTL PCEE_NTBCTL Non Transparent Bridge Control 0x078 on page 10 122...

Page 236: ...ssage 0 1 2 3 0x0C8 0D4 on page 10 137 0x0CC DWord PCEE_OUTMSG1 PCEE_OUTMSG 0 1 2 3 Outbound Message 0 1 2 3 0x0C8 0D4 on page 10 137 0x0D0 DWord PCEE_OUTMSG2 PCEE_OUTMSG 0 1 2 3 Outbound Message 0 1...

Page 237: ...21C on page 10 151 0x220 DWord PCEE_BARTLIMIT2 PCEE_BARTLIMIT2 BAR 2 Translated Limit Address 0x220 on page 10 151 0x224 DWord PCEE_BARTLIMIT3 PCEE_BARTLIMIT3 BAR 3 Translated Limit Address 0x224 on p...

Page 238: ...5 VGAS RO 0x0 VGA Palette Snoop Not applicable 6 PERRE RW 0x0 Parity Error Enable The Master Data Parity Error bit is set in the PCI Status register if this bit is set and the non transparent bridge...

Page 239: ...t or completion received 10 9 DEVT RO 0x0 DEVSEL TIming Not applicable 11 STAS RO 0x0 Signalled Target Abort Not applicable 12 RTAS RW1C 0x0 Received Target Abort This bit is set when the non trans pa...

Page 240: ...Description 7 0 INTF RO 0x00 Interface No standard interface defined 15 8 SUB RO 0x80 Sub Class Code This value indicates that the device is classified as other 23 16 BASE RO 0x06 Base Class Code This...

Page 241: ...x0 addr32 32 bit addressing Located in lower 4 GB address space 0x1 reserved reserved 0x2 addr64 64 bit addressing 0x3 reserved reserved 3 PREF RO Prefetchable If the MEMSI field selects memory this f...

Page 242: ...at 0x0 addr32 32 bit addressing Located in lower 4 GB address space 0x1 reserved reserved 0x1 reserved reserved 0x3 reserved reserved 3 PREF RO Prefetchable If the MEMSI field selects memory this fiel...

Page 243: ...always zero The value of this field is determined by the PREF field in the BARSETUP2 register 0x0 nonprefetch non prefetchable 0x1 prefetch prefetchable 31 4 BADDR RW 0x0 Base Address This field speci...

Page 244: ...by the MEMSI field in the BARSETUP3 register 0x0 nonprefetch non prefetchable 0x1 prefetch prefetchable 31 4 BADDR RW 0x0 Base Address This field specifies the address bits to be used by the non tran...

Page 245: ...d identifies the subsystem Bit Field Field Name Type Default Value Description 7 0 CAPPTR RO 0x40 Capabilities Pointer This field specifies a pointer to the head of the capabilities structure Bit Fiel...

Page 246: ...lue contained in Serial EEPROM may override this default value 24 SLOT RWL 0x0 Slot Implemented This bit is set when the PCI Express link associated with this Port is connected to a slot 29 25 IMN RO...

Page 247: ...ride this default value 14 PIP RO 0x0 Power Indicator Present When set this bit indicates that a Power Indicator is implemented on the card module The value contained in Serial EEPROM may override thi...

Page 248: ...e ment this capability 11 ENS RW 0x0 Enable No Snoop The non transparent bridge does not generate transactions with the No Snoop bit set and passes transactions through the bridge with the No Snoop bi...

Page 249: ...ired to 2 5 Gbps 9 4 MAXLNKWDTH RO 0x8 Maximum Link Width This field is hardwired to 0x8 11 10 ASPMS RO 0x01 Active State Power Management This field is hardwired to indicate L0s entry supported Howev...

Page 250: ...t applicable for endpoints 12 SCLK RO 0x0 Slot Clock Configuration Not applicable for virtual links 15 13 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 7 0 CAPID R...

Page 251: ...emory write transaction If the contents of this field are non zero then 64 bit address is used in the MSI memory write transaction If the contents of this field are zero then the 32 bit address specif...

Page 252: ...When the opposite side is set to not ready all configuration transactions received on the opposite side of the non transparent bridge are responded to with a configuration request retry status complet...

Page 253: ...bit is set in this register and a fundament or hot reset is detected on the opposite side of the non transparent bridge This field is only relevant for the internal side of the non transparent bridge...

Page 254: ...ion is received by the opposite side of the non transparent bridge that does match the bus device function of an entry in the mapping table 5 MTAERR RW1C 0x01 Mapping Table Access Error This bit is se...

Page 255: ...e 0x1 io I O space 2 1 TYPE RW 0x01 Address Select This field determines the value reported in the TYPE field of the corresponding BAR and selects the address space decoding used when memory space is...

Page 256: ...the SIZE field to a value less than four results in all bits in the corresponding BAR BADDR field to take on a read only zero value that effectively disables the BAR The smallest memory size that may...

Page 257: ...et by external fundamental reset or internal external hot reset Bit Field Field Name Type Default Value Description 0 MEMSI RW 0x01 MEMSI Select This field determines the MEMSI type returned in the ME...

Page 258: ...d Corresponding bits less than the SIZE field and greater than or equal to four always return a value of zero when read and cannot be modified Setting the SIZE field to a value less than four results...

Page 259: ...onding BAR 0x0 memory memory space 0x1 io I O space 2 1 TYPE RW 0x01 Address Select This field determines the value reported in the TYPE field of the corresponding BAR and selects the address space de...

Page 260: ...the SIZE field to a value less than four results in all bits in the corresponding BAR BADDR field to take on a read only zero value that effectively disables the BAR The smallest memory size that may...

Page 261: ...et by external fundamental reset or internal external hot reset Bit Field Field Name Type Default Value Description 0 MEMSI RW 0x01 MEMSI Select This field determines the MEMSI type returned in the ME...

Page 262: ...the BAR BADDR field that corre spond to PCI Express address bits greater than or equal to the SIZE field to be modified Corresponding bits less than the SIZE field and greater than or equal to four a...

Page 263: ...corresponding BAR 32 bit addressing is always selected 3 PREF RO 0x0 Prefetchable Select This field determines the value reported in the PREF field of the corresponding BAR Non prefetchable space is...

Page 264: ...rmed when the PTCDATA regis ter is written 0x0 read configuration read 0x1 write configuration write 1 Not reset by external fundamental reset or internal external hot reset Bit Field Field Name Type...

Page 265: ...ion Status This field contains the completion status of the last punch through configuration transaction and is valid only when the DONE bit in this register is set 0x0 sc successful completion 0x1 ur...

Page 266: ...ng table entry pointed to by the ADDR field in the MTADDR register Writing this field updates the mapping table entry pointed to by the ADDR field Only DWord accesses are supported to this register No...

Page 267: ...T proprietary PCI PCI X or PCI Express capability The value of 0x2 identifies this as a non transparent bridge communications capability structure Bit Field Field Name Type Default Value Description 3...

Page 268: ...located in PCI configuration space on the opposite side of the of the non transparent bridge Bit Field Field Name Type Default Value Description 31 0 OUTDBELL RW 0x0 Outbound Doorbell Each bit in this...

Page 269: ...pt Control 0 INTCTL0 register 6 OSPSTATEM RW1C 0x0 Opposite Side Power State Modification This bit is set whenever a modification is made to the PSTATE field in the PMCSR register on the opposite side...

Page 270: ...e INTB assertion and negation mes sages 0x4 int_c generate INTC assertion and negation mes sages 0x5 int_d generate INTD assertion and negation mes sages 0x6 though 0x8 reserved reserved 5 3 INMSG1 RW...

Page 271: ...n and negation mes sages 0x5 int_d generate INTD assertion and negation mes sages 0x6 though 0x8 reserved reserved 11 9 INMSG3 RW 0x0 Inbound Message 3 Configuration This field encodes the action take...

Page 272: ...nd negation mes sages 0x5 int_d generate INTD assertion and negation mes sages 0x6 though 0x7 reserved reserved 17 15 OSRD RW 0x0 Opposite Side Reset Detected Configuration This field encodes the acti...

Page 273: ...NTA assertion and negation mes sages 0x3 int_b generate INTB assertion and negation mes sages 0x4 int_c generate INTC assertion and negation mes sages 0x5 int_d generate INTD assertion and negation me...

Page 274: ...rmine the current power state and to set a new power state 0x0 d0 D0 state 0x1 d1 D1 state not supported by the PES16NT2 and reserved 0x2 d2 D2 state not supported by the PES16NT2 and reserved 0x3 d3...

Page 275: ...guration Data A read from this field will return the configuration space register value pointed to by the ECF GADDR register A write to this field will update the con tents of the configuration space...

Page 276: ...rdless of the value of this field an MSI is only sent when the Enable EN bit is set in the MSICAP register Similarly and INTx message is only sent if not disabled by the INTXD bit in the PCICMD regist...

Page 277: ...ion and negation mes sages 0x5 int_d generate INTD assertion and negation mes sages 0x6 though 0x8 reserved reserved 8 6 PBLINKUP RW 0x0 Port B Link Up Configuration This field encodes the action take...

Page 278: ...on and negation mes sages 0x5 int_d generate INTD assertion and negation mes sages 0x6 though 0x8 reserved reserved 14 12 PCLINKUP RW 0x0 Port C Link Up Configuration This field encodes the action tak...

Page 279: ...PCICMD register The action i e this field should not be modified while the corresponding bit is set Modifying the action when the cor responding bit is set produces undefined results 0x0 disabled int...

Page 280: ...ttribute 2 FNS RW 0x0 Sticky Force No Snoop When this bit is set all TLPs in which the no snoop attribute is applicable are modified as dic tated by the No Snoop Modification NSM field in this reg ist...

Page 281: ...address for transactions that map through BAR1 of the non transparent bridge A translation fails the limit test if the address is greater than the value specified in this field Bit Field Field Name T...

Page 282: ...TB upstream port failover is in progress Modifying this field while an upstream port failover is in progress produces undefined results The initial value of this field depends on the selected switch o...

Page 283: ...ed 6 IDHRSTPROP RW 0x0 Sticky Internal Hierarchy Disable Hot Reset Propagation When this bit is set hot resets received on the upstream port are ignored 7 EDHRSTPROP RW 0x0 Sticky External Hierarchy D...

Page 284: ...IDT Non Transparent Mode Operation PES16NT2 User Manual 10 154 April 15 2008 Notes...

Page 285: ...S16NT2 Test Access Point The system logic utilizes a 16 state TAP controller a six bit instruction register and five dedicated pins to perform a variety of functions The primary use of the JTAG TAP Co...

Page 286: ...active low Asynchronous reset for JTAG TAP controller internal pull up JTAG_TCK Input JTAG Clock Test logic clock JTAG_TMS and JTAG_TDI are sampled on the rising edge JTAG_TDO is output on the fallin...

Page 287: ...nter face PEALREV I PEARN 7 0 I PEARP 7 0 I PEATN 7 0 O PEATP 7 0 O PECLREV I PECRN 7 0 I PECRP 7 0 I PECTN 7 0 O PECTP 7 0 O PEREFCLKN 1 0 I PEREFCLKP 1 0 I REFCLKM I SMBus MSMBADDR 4 1 I MSMBCLK I O...

Page 288: ...nables Therefore the SAMPLE PRELOAD instruction must first be used to load suitable values into the boundary scan cells so that inappropriate values are not driven out onto the system pins All of the...

Page 289: ...ter allows an instruction to be shifted serially into the device at the rising edge of JTAG_TCK The instruction is then used to select the test to be performed or the test register to be accessed or b...

Page 290: ...e rapid testing of a given device all other devices are put into BYPASS mode Instruction Definition Opcode EXTEST Mandatory instruction allowing the testing of board level interconnec tions Data is ty...

Page 291: ...contains a Device ID register it must also contain a BYPASS register The only difference is that the BYPASS register will not be the default register selected during the TAP controller reset When the...

Page 292: ...terfere with normal system operation the TAP controller should be forced into the Test Logic Reset controller state by continuously holding JTAG_TRST_N low and or JTAG_TMS high when the chip is in nor...

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