IDT 89HPES16NT2, User Manual

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IDT SMBus Interfaces
PES16NT2 User Manual 6 - 3 April 15, 2008
Notes
Bit
Field
Field
Name
Type
Default
Value
Description
15:0 MSMBCP RW HWINIT Master SMBus Clock Prescalar. This field contains a
clock prescalar value used during master SMBus transac-
tions. The prescalar clock period is equal to 32 ns multi-
plied by the value in this field. When the field is cleared to
zero or one, the clock is stopped.
The initial value of this field is 0x0139 when the master
SMBus is configured to operate in slow mode (i.e., 100
KHz) in the boot configuration and to 0x0053
1
when it is
configured to operate in fast mode (i.e., 400 KHz).
1.
The MSMBCLK low minimum pulse width is equal to half the period programmed in this field. The value of 0x53, which corre-
sponds to ~373 KHz, allows the min low pulse width to be satisfied. In systems where this timing parameter is not critical, the
operating frequency may be increased.
16 MSMBIOM RW 0x0 Master SMBus Ignore Other Masters. When this bit is
set, the master SMBus proceeds with transactions regard-
less of whether it won or lost arbitration.
17 ICHECKSUM RW 0x0 Ignore Checksum Errors. When this bit is set, serial
EEPROM initialization checksum errors are ignored (i.e.,
the checksum always passes).
19:18 SSMBMODE RW 0x0 Slave SMBus Mode. The slave SMBus contains internal
glitch counters on the SSMBCLK and SSMBDAT signals
that wait approximately 1 µS before sampling or driving
these signals. This field allows the glitch counter time to be
reduced or entirely removed. In some systems, this may
permit high speed slave SMBus operation.
0x0 - (normal) Slave SMBus normal mode. Glitch counters
operate with 1 µS delay.
0x1 - (fast) Slave SMBus interface fast mode. Glitch
counters operate with 100 nS delay.
0x2 - (disabled) Slave SMBus interface with glitch
counters disabled. Glitch counters operate with zero
delay which effectively removes them.
0x3 - reserved.
21:20 MSMBMODE RW 0x0 Master SMBus Mode. The master SMBus contains inter-
nal glitch counters on the MSMBCLK and MSMBDAT sig-
nals that wait approximately 1 µS before sampling or
driving these signals. This field allows the glitch counter
time to be reduced or entirely removed. In some systems,
this may permit high speed master SMBus operation.
0x0 - (normal) Master SMBus normal mode. Glitch
counters operate with 1 µS delay.
0x1 - (fast) Master SMBus interface fast mode. Glitch
counters operate with 100 nS delay.
0x2 - (disabled) Master SMBus interface with glitch
counters disabled. Glitch counters operate with zero
delay which effectively removes them.
0x3 - reserved.
31:22 Reserved RO 0x0 Reserved field.
Table 6.2 SMBUSCTL - SMBus Control