IDT 89HPES16NT2, User Manual

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Notes
PES16NT2 User Manual 1 April 15, 2008
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About This Manual
Introduction
This user manual includes hardware and software information on the 89HPES16NT2, a member of
IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect
standard.
Finding Additional Information
Information not included in this manual such as mechanicals, package pin-outs, and electrical character-
istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com)
as well as through your local IDT sales representative.
Content Summary
Chapter 1, “PES16NT2 Device Overview,” provides a complete introduction to the performance capa-
bilities of the 89HPES16NT2. Included in this chapter is a summary of features for the device as well as a
system block diagram and pin description.
Chapter 2, “Clocking, Reset, and Initialization,” provides a description of the two differential refer-
ence clock inputs that are used internally to generate all of the clocks required by the internal switch logic
and the SerDes.
Chapter 3, “Link Operation,” describes the operation of the link feature including polarity inversion,
link width negotiation, and lane reversal.
Chapter 4, “Switch Operation,” discusses the procedure for forwarding PCIe® TLPs between switch
ports.
Chapter 5, “Power Management,” describes the power management capability structure located in the
configuration space of each PCI-PCI bridge in the PES16NT2.
Chapter 6, “SMBus Interfaces,” describes the operation of the 2 SMBus interfaces on the PES16NT2.
Chapter 7, “NTB Upstream Port Failover,” describes the NTB upstream port failover mechanism that
enables the construction of fault tolerant systems.
Chapter 8, “General Purpose I/O,” describes how the eight General Purpose I/O (GPIO) pins may be
individually configured as general purpose inputs, general purpose outputs, or alternate functions
Chapter 9, “Transparent Mode Operation,” describes how the PES16NT2 can be configured during a
fundamental reset to operate in transparent mode or transparent mode with serial EEPROM initialization.
Chapter 10, “Non-Transparent Mode Operation,” describes how the PES16NT2 can be configured
during a fundamental reset to operate in non-transparent mode or non-transparent mode with serial
EEPROM initialization.
Chapter 11, “JTAG Boundary Scan, ” discusses an enhanced JTAG interface, including a system logic
TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.
Signal Nomenclature
To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms
assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or
true, independent of whether that level is represented by a high or low voltage. The term negate or negation
is used to indicate that a signal is inactive or false.