IDT 89HPES16NT2, User Manual

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IDT Non-Transparent Mode Operation
PES16NT2 User Manual 10 - 10 April 15, 2008
Notes
Configuration Space
Associated with the internal and external NTB endpoints is a 4 KB PCIe configuration space containing
a Type 0 header. The organization of these configuration spaces is described in section NTB Endpoint
Configuration Space Organization on page 10-55. The NTB configuration spaces are symmetric, meaning
that the same fields are located in the locations on both sides of the NTB.
Internal NTB endpoint configuration space registers may be configured by the internal root by
performing configuration read and write operations. External NTB endpoint configuration space registers
may be configured by the external root by performing configuration read and write operations.
Registers associated with the internal or external NTB endpoints occupy the bottom 2 KB of their config-
uration space. The upper 2KB of each endpoint’s configuration space contains the configuration space of
the endpoint associated with the opposite side of the NTB. Thus, an internal root may configure any
external endpoint register simply by adding a 2 KB offset and referencing the internal NTB endpoint’s
configuration space. The external root has a similar capability.
The crosscoupling of NTB endpoint configuration spaces is graphically illustrated in Figure 10.5.
Software should ensure that there are four or less outstanding configuration transactions to an NTB
configuration space. Exceeding this number of outstanding transactions may result in completions being
dropped.
In some systems it may desirable to prevent modification of NTB configuration by endpoints on the
opposite side of the NTB using configuration transactions. When the Opposite Side Configuration Protec-
tion (OSCFGPROT) bit is set in the Non-Transparent Bridge Control (NTBCTL) register, access to the non-
transparent bridge configuration capability structure is disabled for this side as well as for the opposite side
using a 2KB offset into the configuration window. This means that reading any register in this capability
structure, except the NTBCFGC register, returns a value of zero and all writes are ignored. NTBCFGC
returns it’s default value regardless of the setting of the OSCFGPROT field, allowing normal traversal of the
capability structure.
Figure 10.5 Non-Transparent Bridge Configuration Window
0x000
Configuration Space of
PCI Config
Space
0x100
PCI Express
Extended
Config Space
0x800
PCI Config
Space
0x900
PCI Express
Extended
0xFFF
Config Space
0x000
PCI Config
Space
PCI Express
Extended
Config Space
PCI Config
Space
PCI Express
Extended
Config Space
0x100
0x800
0x900
0xFFF
External
Non-Transparent
Bridge
Configuration
Space
Internal
Non-Transparent
Bridge
Configuration
Space
External
Non-Transparent
Bridge
Configuration
Window
Internal
Non-Transparent
Bridge
Configuration
Window
Internal Non-Transparent
Bridge Endpoint
Configuration Space of
External Non-Transparent
Bridge Endpoint