IDT 89HPES16NT2, User Manual

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IDT Switch Operation
PES16NT2 User Manual 4 - 6 April 15, 2008
Notes Table 4.4 exhibits the interrupt sources that are aggregated by the switch.
PCI to PCI bridges must map interrupts on the secondary side of the bridge according to the device
number of the device on the secondary side of the bridge. No mapping is performed for the PCI to PCI
bridges corresponding to downstream ports as these ports only connect to device zero. A mapping is
performed for the upstream port (i.e., port A).This mapping is summarized in Table 4.6 for the PES16NT2.
Assert_INTx and Deassert_INTx messages may also be generated by the non-transparent bridge
external endpoint when the switch is configured to operate in non-transparent mode. These interrupt
messages are transmitted out on port C, as that is the direction of the root for the non-transparent bridge
external endpoint.
If a Downstream Port goes to DL_Down status, the INTx virtual wires associated with that port are deas-
serted, and the port A aggregates are updated accordingly. This may result in the upstream port generating
a Deassert_Intx message.
Switch Core Errors
This section lists error conditions that are checked by the switch core. Due to limited buffering of Unsup-
ported Request (UR) completions, it is possible for the PES16NT2 to discard UR completions if errors are
generated faster than UR completions can be transmitted. Even when UR completions are discarded, error
status bits are always correctly updated and an error message is generated.
Due to limited buffering, error messages may be collapsed if errors are generated faster than error
messages can be transmitted. This means that multiple error conditions may result in only a single error
message being generated. However, under no circumstances are error messages discarded.
PCI Compatible
INTx
Interrupt Sources
INTA - External downstream port C (in transparent mode)
- Non-transparent bridge internal endpoint
INTB - External downstream port C (in transparent mode)
- Non-transparent bridge internal endpoint
INTC - External downstream port C (in transparent mode)
- Non-transparent bridge internal endpoint
INTD - External downstream port C (in transparent mode)
- Non-transparent bridge internal endpoint
Table 4.4 PCI Compatible INTx Aggregation
Port A Interrupt Interrupt Sources
1
1.
Port X INTy corresponds to external downstream generated INTy interrupts or INTy in-
terrupts generated by the internal side of the non-transparent bridge (only for port C).
INTA Port C INTD
INTB Port C INTA
INTC Port C INTB
INTD Port C INTC
Table 4.5 PES16NT2 Upstream Port Bridge Interrupt Mapping