IDT 89HPES16NT2, User Manual

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IDT Clocking, Reset, and Initialization Clock Operation
PES16NT2 User Manual 2 - 4 April 15, 2008
Notes
PEALREV Y PCI Express Port A Lane Reverse. When this pin is asserted,
the lanes of PCI Express Port A are reversed. This value may
be overridden by modifying the value of the PALREV bit in the
PA_SWCTL register.
PECLREV Y PCI Express Port C Lane Reverse. When this pin is asserted,
the lanes of PCI Express Port C are reversed. This value may
be overridden by modifying the value of the PCLREV bit in the
PA_SWCTL register.
REFCLKM N PCI Express Reference Clock Mode Select. These signals
select the frequency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
RSTHALT Y Reset Halt. When this signal is asserted during a PCI Express
fundamental reset, the PES16NT2 executes the reset proce-
dure and remains in a reset state with the Master and Slave
SMBuses active. This allows software to read and write regis-
ters internal to the device before normal device operation
begins. The device exits the reset state when the RSTHALT bit
is cleared in the PA_SWCTL register through the SMBus.
The value may be overridden by modifying the RSTHALT bit in
the PA_SWCTL register.
SWMODE[3:0] N Switch Mode. These configuration pins determine the
PES16NT2 switch operating mode.
0x0 - Transparent mode
0x1 -Transparent mode with serial EEPROM initialization
0x2 - Non-transparent mode
0x3 - Non-transparent mode with serial EEPROM initialization
0x4 - Non-transparent failover mode
0x5 - Non-transparent failover mode with serial EEPROM initial-
ization
0x6 through 0xF - Reserved
Signal Type Name/Description
CCLKDS I Common Clock Downstream. When the CCLKDS pin is asserted, it indi-
cates that a common clock is being used between the downstream device
and the downstream port.
CCLKUS I Common Clock Upstream. When the CCLKUS pin is asserted, it indi-
cates that a common clock is being used between the upstream device and
the upstream port.
MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 KHz. This value
may not be overridden.
PENTBRSTN I Non-Transparent Bridge Reset. Assertion of this signal indicates a reset
on the external side of the non-transparent bridge. This signal is only used
when the switch mode selects a non-transparent mode and has no effect
otherwise.
Table 2.3 System Pins (Part 1 of 2)
Signal
May Be
Overridden
Description
Table 2.2 Boot Configuration Vector Signals (Part 2 of 2)