IDT Non-Transparent Mode Operation
PES16NT2 User Manual
10 - 103
April 15, 2008
Notes
PCIE_BARTLIMIT1 - BAR 1 Translated Limit Address (0x21C)
When the MEMSI field in BARSETUP0 is set to memory space (i.e., zero) and the TYPE field is set to
64-bit addressing, BARTLIMIT1 takes on the function of the upper 32-bits of the TLADDR field in
BARTLIMIT0. In this mode, all 32-bits of BARTLIMIT1 may be read and written.
PCIE_BARTLIMIT2 - BAR 2 Translated Limit Address (0x220)
PCIE_BARTLIMIT3 - BAR 3 Translated Limit Address (0x224)
When the MEMSI field in BARSETUP2 is set to memory space (i.e., zero) and the TYPE field is set to
64-bit addressing, BARTLIMIT3 takes on the function of the upper 32-bits of the TLADDR field in
BARTLIMIT2. In this mode, all 32-bits of BARTLIMIT1 may be read and written.
Bit
Field
Field
Name
Type
Default
Value
Description
3:0
Reserved
RO
0x0
Reserved field.
31:4
TLADDR
RW
0xFFF_FFFF
1
1.
Not reset by external fundamental reset or internal/external hot reset
Translated Limit Address.
This field specifies the trans-
lated limit address for transactions that map through BAR1
of the non-transparent bridge.
A translation fails the limit test if the address is greater than
the value specified in this field.
Bit
Field
Field
Name
Type
Default
Value
Description
3:0
Reserved
RO
0x0
Reserve field.
31:4
TLADDR
RW
0xFFF_FFFF
1
1.
Not reset by external fundamental reset or internal/external hot reset
Translated Limit Address.
This field specifies the trans-
lated limit address for transactions that map through BAR2
of the non-transparent bridge.
When 64-bit addressing is selected, the translated limit
address consists of the value in this field together with the
upper 32 bits of the address contained in the BARTBASE3
register.
A translation fails the limit test if the address is greater than
the value specified in this field.
Bit
Field
Field
Name
Type
Default
Value
Description
3:0
Reserved
RO
0x0
Reserved field.
31:4
TLADDR
RW
0xFFF_FFFF
1
1.
Not reset by external fundamental reset or internal/external hot reset
Translated Limit Address.
This field specifies the trans-
lated limit address for transactions that map through BAR3
of the non-transparent bridge.
A translation fails the limit test if the address is greater than
the value specified in this field.
Summary of Contents for 89HPES16NT2
Page 14: ...DT List of Figures PES16NT2 User Manual viii April 15 2008 Notes...
Page 20: ...IDT Register List PES16NT2 User Manual xiv April 15 2008 Notes...
Page 32: ...IDT PES16NT2 Device Overview PES16NT2 User Manual 1 12 April 15 2008 Notes...
Page 50: ...IDT Link Operation PES16NT2 User Manual 3 6 April 15 2008 Notes...
Page 62: ...IDT Power Management PES16NT2 User Manual 5 4 April 15 2008 Notes...
Page 78: ...IDT SMBus Interfaces PES16NT2 User Manual 6 16 April 15 2008 Notes...
Page 83: ...IDT NTB Upstream Port Failover PES16NT2 User Manual 7 5 April 15 2008 Notes...
Page 84: ...IDT NTB Upstream Port Failover PES16NT2 User Manual 7 6 April 15 2008 Notes...
Page 130: ...IDT Transparent Mode Operation PES16NT2 User Manual 9 44 April 15 2008 Notes...
Page 284: ...IDT Non Transparent Mode Operation PES16NT2 User Manual 10 154 April 15 2008 Notes...