IDT 89HPES16NT2, User Manual

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IDT Transparent Mode Operation
PES16NT2 User Manual 9 - 27 April 15, 2008
Notes PA_PMCSR - PCI Power Management Control and Status (0x074)
PA_PMPC - PCI Power Management Proprietary Control (0x078)
Mode1
Bit
Field
Field
Name
Type
Default
Value
Description
1:0 PSTATE RW 0x0 Power State . This field is used to determine the current
power state and to set a new power state.
0x0 - (d0) D0 state
0x1 - (d1) D1 state (not supported by PES16NT2 and
reserved)
0x2- (d2) D2 state (not supported by PES16NT2 and
reserved)
0x3 - (d3) D3
hot
state
7:2 Reserved RO 0x0 Reserved field.
8 PMEE RW 0x0
Sticky
PME Enable. When this bit is set, PME message genera-
tion is enabled for the port.
If a hot plug wake-up event is desired when exiting the
D3
cold
state, then this bit should be set during serial
EEPROM initialization.
A hot reset does not result in modification of this field.
12:9 DSEL RO 0x0 Data Select. The optional data register is not implemented.
14:13 DSCALE RO 0x0 Data Scale. The optional data register is not implemented.
15 PMES RW1C 0x0
Sticky
for port C
RO 0x0 for
port A
PME Status. This bit is set if a PME is generated by the
port even if the PMEE bit is cleared. This bit is not set when
the bridge is propagating a PME message but the port is
not itself generating a PME.
21:16 Reserved RO 0x0 Reserved field.
22 B2B3 RO 0x0 B2/B3 Support. Does not apply to PCI Express.
23 BPCCE RO 0x0 Bus Power/Clock Control Enable. Does not apply to PCI
Express.
31:24 DATA RO 0x0 Data. This optional field is not implemented.
Bit
Field
Field
Name
Type
Default
Value
Description
15:0 L1ET RW 0x3E8 L1 Entry Timer. This field specifies the L1 entry timer
value for the related port transmitter. If all L1 entry condi-
tions are met for the specified amount of time, then the
transmitter port enters L1.
This field is used by the upstream ports and ignored by
downstream ports.
The timer value is specified in the number 1 µS clock
cycles. The default value corresponds to 1 mS