IDT 89HPES16NT2, User Manual

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IDT Non-Transparent Mode Operation
PES16NT2 User Manual 10 - 8 April 15, 2008
Notes
Doorbell Registers
The internal and external endpoints each have an Inbound Doorbell (INDBELL) and Outbound Doorbell
(OUTDBELL) register. The OUTDBELL register may be read and written while INDBELL register is read
and cleared. The doorbell registers provide 32 doorbells in each direction through the non-transparent
bridge. When a bit is set in the OUTDBELL register, the corresponding bit is set in the INDBELL register on
the opposite side of the NTB. When any bit in the INDBELL register is set, then the INDBELL bit is set in the
INTSTS register on that side of the non-transparent bridge and may be used to generate an interrupt.
Note that the INDBELL bits are of type RW1C and are set only when a bit in the corresponding OUTD-
BELL register transitions from a zero to a one.
Scratchpad Registers
There are two Scratchpad (SCRATCHPAD[0..1]) registers shared between the internal and external
sides of the non-transparent bridge. Writing to a scratchpad register immediately modifies its value on both
sides of the non-transparent bridge. There are no interrupts or other notification associated with scratchpad
register modifications. Scratchpad registers may not be accessed using the Extended Configuration Space
Data (ECFGDATA) register. The behavior of scratchpad register accesses using this mechanism is unde-
fined.
Interrupts
There are 13 events that may cause an interrupt to be generated by a non-transparent bridge endpoint.
Four of these correspond to the inbound message registers, one with the inbound doorbell register, one
with detection of a fundamental or hot reset on the opposite side of the non-transparent bridge, one with
modification of the power management state on the opposite side of the non-transparent bridge, and six
associated with link status.
Internal NTB endpoint interrupts and MSIs are routed upstream to the internal root on port A while
external NTB endpoint interrupts and MSIs are sent out on the link associated with the non-transparent
bridge (i.e., port C link). Each interrupt source has an associated bit in the Interrupt Status (INTSTS)
register. Associated with each bit in the INTSTS register is a configuration field in the Interrupt Control 0
(INTCTL0) or Interrupt Control 1 (INTCTL1) register. This field determines how the interrupt is handled.
Each interrupt bit may be individually configured to generate an MSI, an ASSERT_INTx/DEASSERT_INTx
message, or may be disabled (i.e., masked).
When an interrupt source is configured to generate an MSI, an MSI is generated if the corresponding
source bit is set and the MSI is enabled (i.e., the EN bit is set in the MSICAP register). When an interrupt
source is configured to generate INTx messages, ASSERT_INTx/DEASSERTx messages are generated if
the corresponding source bit is set and endpoint interrupts are not disabled (i.e., the INTXD bit is cleared in
the PCICMD register).
Note that a function is prohibited by the PCI 2.3 specification from requesting service via INTx
messages if MSIs are enabled. The NTB endpoints are capable of generating INTx messages even when
MSIs are enabled. It is the responsibility of system software to properly configure the NTB endpoints.
MSI and INTx Message Generation
Each of the status bits in the INTSTS register represents an interrupt source. When an interrupt source
requests service, the corresponding bit in the INTSTS register is set. The action taken (i.e., disabled, INTx,
or MSI) for a particular interrupt source is determined by a corresponding field in the INTCTL0 or INTCTL1
register.
An interrupt source may be mapped to one of the legacy interrupts (INTA, INTB, INTC, or INTD) or to a
single MSI generated by the endpoint.
All of the interrupt sources which are mapped to an MSI are logically ORed to produce an MSI request
value . Whenever the MSI request value transitions from false (i.e., no request) to true, an MSI message is
generated to the address and with the data specified in the MSI capability structure. A new MSI is not
generated until the
MSI request value transitions to false and then again transitions to true. Thus, a non-