IDT Non-Transparent Mode Operation
PES16NT2 User Manual
10 - 11
April 15, 2008
Notes
Memory Mapped Configuration Space
In PCIe only the root may perform configuration space read and write operations. Since the interpro-
cessor communication facilities are mapped into configuration space, it is desirable to provide a means for
any PCIe master to access configuration space. BAR4 of each NTB endpoint allows the entire 4 KB config-
uration space to be memory mapped into PCIe space allowing any master to access configuration regis-
ters. The organization of this 4 KB memory is the same as that for the corresponding configuration space.
BAR4 memory mapped configuration space may be accessed using byte, word, or doubleword transac-
tions. The behavior of read or write transactions to this space of any other size, including zero, is undefined.
Software should ensure that there are four or less outstanding read transactions to BAR4 mapped memory.
Exceeding this number of outstanding transactions may result in completions being dropped.
In some systems it may desirable to prevent modification of NTB configuration by endpoints on the
opposite side of the NTB using BAR4 mapped memory. When the Opposite Side Configuration Protection
(OSCFGPROT) bit is set in the Non-Transparent Bridge Control (NTBCTL) register, access to the non-
transparent bridge configuration capability structure is disabled for this side as well as for the opposite side
using a 2KB offset into the configuration window. This means that reading any register in this capability
structure, except the NTBCFGC register, returns a value of zero and all writes are ignored. NTBCFGC
returns it’s default value regardless of the setting of the OSCFGPROT field, allowing normal traversal of the
capability structure.
Opposite Side Configuration Requests
The internal endpoint has the capability to generate configuration transactions on the external side of
the NTB. This mechanism, referred to as punch through, is provided to facilitate systems in which there
does not exist a root on the external side of the NTB. The external endpoint is unable to generate configura-
tion transactions on the internal side of the NTB.
To generate a configuration transaction on the external side of the NTB, an internal endpoint or root
should execute the following sequence:
1. Check if the punch through configuration interface is busy by examining the Busy (BUSY) bit in the
Punch Through Configuration Status (PTCSTS) register and wait until the interface is not busy.
2. Configure the operation in the Punch Through Configuration Control (PTCCFG) register.
3. Write to the Punch Through Configuration Data (PTCDATA) register to initiate the configuration read
or write operation as selected by the OP field in the PTCCFG register.
4. Wait for the operation to complete by examining the status of the Done (DONE) bit in the PTCSTS
register.
5. Check the transaction completion status in the Status (STATUS) field of the PTCSTS register. If the
initiated transaction was a read and it successfully completed, then the read result may be read from
the PTCDATA register.
It is possible for a completion to not be generated in response to a punch-through configuration transac-
tion. A punch-through operation may be aborted by writing a one to the DONE bit in the PTCSTS register.
This will cause subsequent completions to be discarded until a new punch-through configuration transac-
tion is generated. This mechanism should only be used when it is certain that a completion is lost and will
never arrive.
Configuration Requests
The port C PCI-PCI bridge, internal NTB and external NTB endpoints all have configuration registers
that may be accessed with Type 0 configuration read and write requests. PCIe allows multiple outstanding
configuration read and write requests. The port C PCI-PCI bridge, internal NTB endpoint and external NTB
endpoints each support a maximum of four outstanding configuration requests. Issuing more than four
outstanding configuration requests to any of these entities may result in configuration requests being
dropped.
Summary of Contents for 89HPES16NT2
Page 14: ...DT List of Figures PES16NT2 User Manual viii April 15 2008 Notes...
Page 20: ...IDT Register List PES16NT2 User Manual xiv April 15 2008 Notes...
Page 32: ...IDT PES16NT2 Device Overview PES16NT2 User Manual 1 12 April 15 2008 Notes...
Page 50: ...IDT Link Operation PES16NT2 User Manual 3 6 April 15 2008 Notes...
Page 62: ...IDT Power Management PES16NT2 User Manual 5 4 April 15 2008 Notes...
Page 78: ...IDT SMBus Interfaces PES16NT2 User Manual 6 16 April 15 2008 Notes...
Page 83: ...IDT NTB Upstream Port Failover PES16NT2 User Manual 7 5 April 15 2008 Notes...
Page 84: ...IDT NTB Upstream Port Failover PES16NT2 User Manual 7 6 April 15 2008 Notes...
Page 130: ...IDT Transparent Mode Operation PES16NT2 User Manual 9 44 April 15 2008 Notes...
Page 284: ...IDT Non Transparent Mode Operation PES16NT2 User Manual 10 154 April 15 2008 Notes...