IDT 89HPES16NT2, User Manual

Page: 212 / 292

IDT Non-Transparent Mode Operation
PES16NT2 User Manual 10 - 82 April 15, 2008
Notes
PCIE_BARTBASE2 - BAR 2 Translated Base Address (0x090)
9:4 SIZE RW 0x0
1
Address Space Size. This field selects the size, in
address bits, of the address space for the corresponding
BAR or BAR pair when 64-bit addressing is selected.
Assuming the size field is set to a valid value, the size of
the address space requested by the BADDR field in the
corresponding BAR is equal to 2
SIZE
or 2
64
when this field
is zero.
Bits in the BAR BADDR field correspond to PCI Express
address bits. For example, bit 0 or the BAR BADDR field
corresponds to PCI Express Address bit 4.
Setting this field to zero allows all bits in the corresponding
BAR BADDR field to be modified (i.e., selects entire 64-bit
address space). Otherwise, setting this SIZE field to a non-
zero value allows bits in the BAR BADDR field that corre-
spond to PCI Express address bits greater than or equal to
the SIZE field to be modified. Corresponding bits less than
the SIZE field and greater than or equal to four always
return a value of zero when read and cannot be modified.
Setting the SIZE field to a value less than four results in all
bits in the corresponding BAR BADDR field to take on a
read-only zero value that effectively disables the BAR.
The smallest memory size that may be requested by PCI
Express is 128 (i.e., SIZE equal to 7) and the largest is 2
32
bytes for 32-bit address space and 2
64
bytes for 64-bit
address space. The smallest I/O size that may be
requested by the PES16NT2 is 16 bytes (i.e., SIZE equal
to 4) while the largest allowed by PCI express is 256 bytes.
The PES16NT2 does not enforce the minimum memory
size or the maximum I/O size in hardware. Therefore, it 128
is the responsibility of the user to ensure that these require-
ments are met.
Setting the SIZE field to a value greater than 32 when then
MEMSI and TYPE fields in this register select I/O space or
32-bit memory space, results in bits greater than 32 being
ignored (i.e., only the TYPE field can enable 64-bit
addressing).
30:10 Reserved RO 0x0 Reserved field.
31 EN RW 0x0
1
BAR Enable. When cleared, the corresponding BAR is dis-
abled and returns a zero when read.
0x0 - (disabled) disabled.
0x1 - (enabled) enabled.
1.
Not reset by external fundamental reset or internal/external hot reset
Bit
Field
Field
Name
Type
Default
Value
Description
3:0 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description