IDT 89HPES16NT2, User Manual

Page: 274 / 292

IDT Non-Transparent Mode Operation
PES16NT2 User Manual 10 - 144 April 15, 2008
Notes
PCEE_PMCSR - PCI Power Management Control and Status (0x0F4)
21 DEVSP RWL 0x0 Device Specific Initialization. The value of zero indicates
that no device specific initialization is required.
24:22 AUXI RO 0x0 AUX Current. not used
25 D1 RO 0x0 D1 Support. This field indicates that the PES16NT2 does
not support D1.
26 D2 RO 0x0 D2 Support. This field indicates that the PES16NT2 does
not support D2.
31:27 PME RO 0x0 PME Support. Non-transparent bridge endpoints never
generate a PME message. This field indicates the power
states in which the port may generate a PME.
Bit
Field
Field
Name
Type
Default
Value
Description
1:0 PSTATE RW 0x0 Power State . This field is used to determine the current
power state and to set a new power state.
0x0 - (d0) D0 state
0x1 -(d1) D1 state (not supported by the PES16NT2 and
reserved)
0x2- (d2) D2 state (not supported by the PES16NT2 and
reserved)
0x3 -(d3) D3
hot
state
7:2 Reserved RO 0x0 Reserved field.
8 PMEE RO 0x0 PME Enable. Non-transparent bridge endpoints never
generate PM_PME messages. Therefore, this bit is hard-
wired to zero.
12:9 DSEL RO 0x0 Data Select. The optional data register is not implemented.
14:13 DSCALE RO 0x0 Data Scale. The optional data register is not implemented.
15 PMES RO 0x0 PME Status. Non-transparent bridge endpoints don’t sup-
port PME notification. Therefore, this bit is hardwired to
zero.
21:16 Reserved RO 0x0 Reserved field.
22 B2B3 RO 0x0 B2/B3 Support. Does not apply to PCI Express.
23 BPCCE RO 0x0 Bus Power/Clock Control Enable. Does not apply to PCI
Express.
31:24 DATA RO 0x0 Data. This optional field is not implemented.
Bit
Field
Field
Name
Type
Default
Value
Description