IDT 89HPES16NT2, User Manual

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IDT Clocking, Reset, and Initialization Clock Operation
PES16NT2 User Manual 2 - 7 April 15, 2008
Notes
Fundamental Reset
A fundamental reset of the entire device may be initiated by one of five conditions:
– A cold reset initiated by a power-on and the assertion of the PCI Express Reset (PERSTN) input
pin.
– A warm reset initiated by the assertion of the PCI Express Reset (PERSTN) input pin while power
is on.
– A warm reset initiated by the writing of a one to the Reset (RST) bit in the Port A Switch Control
(PA_SWCTL) register.
– A warm reset initiated by the writing of a one to the Reset (RST) bit in the Non-Transparent Bridge
Control (NTBCTL) register of the internal side of the non-transparent bridge when the switch is in
a non-transparent operating mode.
– A warm reset initiated by the writing of a one to the Reset (RST) bit in the Non-Transparent Bridge
Control (NTBCTL) register of the external side of the non-transparent bridge when the switch is in
a non-transparent operating mode.
– A warm reset initiated by the assertion of the non-transparent bridge fundamental reset (PENT-
BRSTN) signal when the device is configured to operate in non-transparent mode and the Prop-
agate External Fundamental Reset (PEFR) bit is set in the NTBCTL register of the internal or
external side of the non-transparent bridge.
The PCIe® standard specifies that normal operation should begin within 1.0 second after a fundamental
reset of a device. The reset sequence above guarantees that normal operation will begin within this period
as long as the serial EEPROM initialization process completes within 200 ms. Under normal circumstances,
200 ms is more than adequate to initialize every register in the device even with a Master SMBus operating
frequency of 100 KHz.
Serial EEPROM initialization may cause writes to register fields that initiate side effects such as link
retraining. These side effects are initiated at the point at which the write occurs. Therefore, serial EEPROM
initialization should be structured in a manner so as to ensure proper configuration prior to initiation of these
side effects.
The PES16NT2 provides a reset output signal for each downstream port implemented as a GPIO alter-
nate function. The downstream port C reset output (PECRSTN) signal is an alternate function of GPIO[1].
When a fundamental reset occurs, all of the GPIO pins default to GPIO inputs. Therefore, the downstream
port resets are tri-stated. A system designer should use a pull-down on these signals if they are used as
reset outputs.
Fundamental and hot resets in non-transparent mode are described in section section Non-Transparent
Mode Reset on page 2-9.
The operation of a fundamental reset in Transparent mode with serial EEPROM initialization (i.e.,
SWMODE[3:0] = 0x1) is illustrated in Figure 2.5.
1.
An External Fundamental reset in non-transparent mode with the PEFR bit set in either NTBCTL register is the same
as a fundamental reset. See that column for its behavior.
2.
All registers except those in the NTB configuration capability structure.