7: B
ASIC
I
NSTRUCTIONS
FC5A M
ICRO
S
MART
U
SER
’
S
M
ANUAL
FC9Y-B1268
7-11
TMLO, TIMO, TMHO, and TMSO (Off-Delay Timer)
Four types of timedown off-delay timers are available; 1-sec off-delay timer TMLO, 100-ms off-delay timer TIMO, 10-ms
off-delay timer TMHO, and 1-ms off-delay timer TMSO. A total of 256 on- and off-delay timers can be programmed in a
user program for any type of CPU module. Each timer must be allocated to a unique number T0 through T255.
These instructions are available on upgraded CPU modules with system program version 200 or higher.
Timer
Device Address
Range
Increments
Preset Value
TMLO (1-sec off-delay timer)
T0 to T255
0 to 65535 sec
1 sec
Constant:
0 to 65535
Data registers: D0 to D1999
D2000 to D7999
D10000 to D49999
TIMO (100-ms off-delay timer)
T0 to T255
0 to 6553.5 sec
100 ms
TMHO (10-ms off-delay timer)
T0 to T255
0 to 655.35 sec
10 ms
TMSO (1-ms off-delay timer)
T0 to T255
0 to 65.535 sec
1 ms
The valid device range depends on the CPU module type. For details, see pages 6-1 and 6-2.
The preset value can be 0 through 65535 and designated using a constant or a data register.
TMLO (1-sec Off-delay Timer)
I1
I0
T0
Ladder Diagram (TMLO)
TMLO
4
T0
I0
ON
OFF
T0
ON
OFF
I1
ON
OFF
Q0
ON
OFF
Timing Chart
4 sec
Instruction
Data
LOD
TMLO
LOD
AND
OUT
I0
T0
4
I1
T0
Q0
Program List
Q0
TIMO (100-ms Off-delay Timer)
I1
I0
T1
Ladder Diagram (TIMO)
TIMO
20
T1
I0
ON
OFF
T1
ON
OFF
I1
ON
OFF
Q1
ON
OFF
Timing Chart
Instruction
Data
LOD
TIMO
LOD
AND
OUT
I0
T1
20
I1
T1
Q1
Program List
Q1
2 sec
TMHO (10-ms Off-delay Timer)
I1
I0
T2
Ladder Diagram (TMHO)
TMHO
100
T2
I0
ON
OFF
T2
ON
OFF
I1
ON
OFF
Q2
ON
OFF
Timing Chart
Instruction
Data
LOD
TMHO
LOD
AND
OUT
I0
T2
100
I1
T2
Q2
Program List
1 sec
Q2
TMSO (1-ms Off-delay Timer)
I1
I0
T3
Ladder Diagram (TMSO)
TMSO
500
T3
I0
ON
OFF
T3
ON
OFF
I1
ON
OFF
Q3
ON
OFF
Timing Chart
Instruction
Data
LOD
TMSO
LOD
AND
OUT
I0
T3
500
I1
T3
Q3
Program List
0.5 sec
Q3
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