ICS ELECTRONICS 4809A, Instruction Manual

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3
The Questionable Enable Register enables set Event bits to be included in
the summary output to the Status Byte Register. The following example
enables bits 12 and 13:
STAT:QUES:ENAB #h3000 ‘enables Event bits 12 and 13
Note that the Questionable Event Register has to be cleared after an SRQ
is generated either by reading the register or with the *CLS command. If
the register is not cleared, the event bits will remain set and they will not
generate another SRQ when the input again goes true.
STAT:QUES:COND? ‘reads the questionable inputs
3.4.5 Operation Registers
The 488.2 Operation Registers lets the user read device specific status condi-
tions and detect any changes in the device’s status. The Operation Registers
are similar to the Questionable Registers described in paragraph 3.4.3. In
the 4899A, the Operation Condition Register reports the WTG (Waiting for
Trigger) status and the Local Lockout and Remote GPIB interface states.
The WTG bit is true when the 4899A has been armed and is waiting for
a trigger. The following commands demonstrate some possibilities of the
Operation Registers:
STAT:OPER:PTR 32 ‘enables bit 5 to set on a positive
transition of WTG
STAT:OPER:ENAB 32 ‘enables Event bit 5
STAT:OPER:COND? ‘quires the Operation Condition
Register
3.4.6 Output Queue
The Output Queue is used by the 4899A to send IEEE 488.2 messages
back to the bus controller. These messages are responses to 488.2 and SCPI
queries sent to the unit by the bus controller. The Output Queue reports
a ‘1’ in bit 4 of the Status Byte Register when it contains a message(s) to
be read by the bus controller. Reading the contents of the Output Queue
clears its summary bit. The Output Queue is read by addressing the 4899A
to talk at its GPIB address. If the Output Queue is not read before sending
another query, its contents will be lost and an error reported.
3.4.7 Status Byte Register