Freescale Semiconductor MPC5553, Reference Manual

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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
19-52 Freescale Semiconductor
Figure 19-28 describes the command message format for a read configuration command when interfacing
with the on-chip ADCs. A read configuration command is used to read the contents of the on-chip ADC
registers which are only accessible via command messages. Read configuration commands are
differentiated from write configuration commands by an asserted R/W bit.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
EOQ PAUSE Reserved EB
(0b0)
BN R/W
(0b1)
MESSAGE_TAG Reserved
CFIFO Header ADC Command
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved ADC_REG_ADDRESS
ADC Command
Figure 19-28. Read Configuration Command Message Format for
On-Chip ADC Operation
Table 19-36. On-Chip ADC Field Descriptions: Read Configuration
Bits Name Description
0 EOQ End-of-queue. Asserted in the last command of a command queue to indicate to the
eQADC that a scan of the queue is completed. EOQ instructs the eQADC to reset its
current CFIFO transfer counter value (TC_CF) to 0. Depending on the CFIFO mode
of operation, the CFIFO status will also change upon the detection of an asserted
EOQ bit on the last transferred command. See
Section 19.4.3.5, “CFIFO Scan Trigger
Modes ,” for details.
0 Not the last entry of the command queue.
1 Last entry of the command queue.
Note: If both the pause and EOQ bits are asserted in the same command message
the respective flags are set, but the CFIFO status changes as if only the EOQ bit were
asserted.
1 PAUSE Pause bit. Allows software to create sub-queues within a command queue. When the
eQADC completes the transfer of a command with an asserted pause bit, the CFIFO
enters the WAITING FOR TRIGGER state. Refer to
Section 19.4.3.6.1, “CFIFO
Operation Status ,” for a description of the state transitions. The pause bit is only valid
when CFIFO operation mode is configured to single or continuous-scan edge trigger
mode.
0 Do not enter WAITING FOR TRIGGER state after transfer of the current command
message.
1 Enter WAITING FOR TRIGGER state after transfer of the current command
message.
Note: If both the pause and EOQ bits are asserted in the same command message
the respective flags are set, but the CFIFO status changes as if only the EOQ bit were
asserted.
2–4 — Reserved.
5 EB External buffer bit. This bit should always be cleared for messages sent to an on-chip
ADC.
0 Command is sent to an internal command buffer.
1 Command is sent to an external command buffer.