Freescale Semiconductor MPC5553, Reference Manual

Page: 502 / 1208

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 12-53
If no device responds by asserting TA within the programmed timeout period (BMT in EBI_BMCR) after
the EBI initiates the bus cycle, the internal bus monitor (if enabled) asserts TEA to terminate the cycle. An
external device may also drive TEA when it detects an error on an external transaction. TEA assertion
causes the cycle to terminate and the processor to enter exception processing for the error condition. To
properly control termination of a bus cycle for a bus error with external circuitry, TEA must be asserted at
the same time or before (external) TA is asserted. TEA must be negated before the second rising edge after
it was sampled asserted in order to avoid the detection of an error for the following bus cycle initiated.
TEA is only driven by the EBI during the cycle where the EBI is asserting TEA and the cycle immediately
following this assertion (for fast negation). During all other cycles, the EBI relies on a weak internal
pull-up to hold TEA negated. This allows an external device to assert TEA when it needs to indicate an
error. External devices must follow the same protocol as the EBI, only driving TEA during the assertion
cycle and 1 cycle afterwards for negation.
NOTE
In the case where an external master asserts TEA to timeout a transaction to
an internal address on this MCU, the EBI has no way to terminate the
transfer internally. Therefore, any subsequent TS assertions by the external
master are ignored by the EBI until the original transfer has completed
internally and the EBI has returned to an idle state. The expectation is that
the internal slaves will always respond with either valid data or an error
indication within a reasonable period of time to avoid hanging the system.
When TEA is asserted from an external source, the EBI uses a latched version of TEA (1 cycle delayed)
to help make timing at high frequencies. This means that for any accesses where the EBI drives TA (chip
select accesses and external master accesses to EBI), a TEA assertion that occurs 1 cycle before or during
the last TA of the access could be ignored by the EBI, because it will have completed the access internally
before it detects the latched TEA assertion. This means that non-burst chip select accesses with no wait
states (SCY = 0) cannot be reliably terminated by external TEA. If external error termination is required
for such a device, the EBI must be configured for SCY

1.
NOTE
For the cases discussed above where TEA could be ignored, this is not
guaranteed. For some small access cases (which always use chip select and
internally-driven TA), a TEA that occurs 1 cycle before or during the TA
cycle or for SCY = 0 may in fact lead to terminating the cycle with error.
However, proper error termination is not guaranteed for these cases, so TEA
must always be asserted at least 2 cycles before an internally-driven TA
cycle for proper error termination.
External TEA assertion that occurs during the same cycle that TS is asserted by the EBI is always treated
as an error (terminating the access) regardless of SCY.
Table 12-23 summarizes how the EBI recognizes the termination signals provided from an external device.
Table 12-23. Termination Signals Protocol
TEA
1
TA
1
Action
Negated Negated No Termination
Asserted X Transfer Error Termination
Negated Asserted Normal Transfer Termination