Freescale Semiconductor MPC5553, Reference Manual

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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 24-3
24.1.2 Overview
The JTAGC provides the means to test chip functionality and connectivity while remaining transparent to
system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the
IEEE 1149.1-2001 standard. In addition, instructions can be executed that allow the Test Access Port
(TAP) to be shared with other modules on the MCU. All data input to and output from the JTAGC is
communicated in serial format.
24.1.3 Features
The JTAGC is compliant with the IEEE 1149.1-2001 standard, and supports the following features:
• IEEE 1149.1-2001 Test Access Port (TAP) interface.
— 4 pins (TDI, TMS, TCK, and TDO), See
Section 24.2, “External Signal Description .”
• A JCOMP input that provides the ability to share the TAP.
• A 5-bit instruction register that supports several IEEE 1149.1-2001 defined instructions, as well as
several public and private MPC5553/MPC5554 specific instructions.
• Four test data registers: a bypass register, a boundary scan register, and a device identification
register. The size of the boundary scan register is 464 bits (MPC5554) and 392 bits (MPC5553).
• A TAP controller state machine that controls the operation of the data registers, instruction register
and associated circuitry.
24.1.4 Modes of Operation
The JTAGC uses JCOMP and a power-on reset indication as its primary reset signals. Several IEEE
1149.1-2001 defined test modes are supported, as well as a bypass mode.
24.1.4.1 Reset
The JTAGC is placed in reset when the TAP controller state machine is in the TEST-LOGIC-RESET state.
The TEST-LOGIC-RESET state is entered upon the assertion of the power-on reset signal, negation of
JCOMP, or through TAP controller state machine transitions controlled by TMS. Asserting power-on reset
or negating JCOMP results in asynchronous entry into the reset state. While in reset, the following actions
occur:
• The TAP controller is forced into the test-logic-reset state, thereby disabling the test logic and
allowing normal operation of the on-chip system logic to continue unhindered.
• The instruction register is loaded with the IDCODE instruction.
In addition, execution of certain instructions can result in assertion of the internal system reset. These
instructions include EXTEST, CLAMP, and HIGHZ.
24.1.4.2 IEEE 1149.1-2001 Defined Test Modes
The JTAGC supports several IEEE 1149.1-2001 defined test modes. The test mode is selected by loading
the appropriate instruction into the instruction register while the JTAGC is enabled. Supported test
instructions include EXTEST, HIGHZ, CLAMP, SAMPLE and SAMPLE/PRELOAD. Each instruction
defines the set of data registers that may operate and interact with the on-chip system logic while the
instruction is current. Only one test data register path is enabled to shift data between TDI and TDO for
each instruction.