Freescale Semiconductor MPC5553, Reference Manual

Page: 195 / 1208

System Interface Unit (SIU)
MPC5553/MPC5554 Microcontroller Reference Manual,
Rev. 5
6-16 Freescale Semiconductor
6.3.1.7 Overrun Status Register (SIU_OSR)
The SIU_OSR contains flag bits that record an overrun.
6.3.1.8 Overrun Request Enable Register (SIU_ORER)
The SIU_ORER contains bits to enable an overrun if the corresponding flag bit is set in the SIU_OSR. If
any overrun request enable bit and the corresponding flag bit are set, the single combined overrun request
from the SIU to the interrupt controller is asserted.
Table 6-10. SIU_DIRSR Field Descriptions
Register Bit Range
Field Name
Function
0–27
Reserved.
28–31
DIRSn
DMA/interrupt request select n. Selects between a DMA or interrupt request when an
edge-triggered event occurs on the corresponding IRQ[n] pin.
0 Interrupt request is selected.
1 DMA request is selected.
Address: Base + 0x0020 Access: Read/ Write[16:31]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Address: Base + 0x0020 Access: Read/ Write[16:31]
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
OVF
15
OVF
14
OVF
13
OVF
12
OVF
11
OVF
10 OVF9 OVF8 OVF7 OVF6 OVF5 OVF4 OVF3 OVF2 OVF1 OVF0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 6-9. Overrun Status Register (SIU_OSR)
Table 6-11. SIU_OSR Field Descriptions
Register Bit Range
Field Name
Function
0–15
Reserved.
16–31
OVFn
Overrun flag n. This bit is set when an overrun occurs on the corresponding IRQn pin.
0 No overrun has occurred on the corresponding IRQ[n] pin.
1 An overrun has occurred on the corresponding IRQ[n] pin.