System Interface Unit (SIU)
MPC5553/MPC5554 Microcontroller Reference Manual,
Rev. 5
Freescale Semiconductor
6-67
6.3.1.12.66
Pad Configuration Register 110 (SIU_PCR110)
The SIU_PCR110 register controls the pin function, direction, and static electrical attributes of the
PCSB[5]_PCSC[0]_GPIO[110] pin.
Figure 6-78. PCSB[5]_PCSC[0]_GPIO[110] Pad Configuration Register (SIU_PCR110)
Refer to
for bit field definitions.
6.3.1.12.67
Pad Configuration Register 111–112 (SIU_PCR111–SIU_PCR112)
The SIU_PCR111–SIU_PCR112 registers control the pin function, direction, and static electrical
attributes of the ETRIG[0:1]_GPIO[111:112] pins.
Figure 6-79. ETRIG[0:1]_GPIO[111:112] Pad Configuration Register (SIU_PCR111–SIU_PCR112)
Refer to
for bit field definitions.
Address: Base + 0x011C
Access: Read / write[4:7, 10:15]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
PA
OBE
1
1
When configured as PCSB[5], the OBE bit has no effect. When configured as PCSC[0], set the OBE bit to 1 for master
operation, and clear it to 0 for slave operation. When configured as GPO, set the OBE bit to 1.
IBE
2
2
When configured as PCSC[0] in slave operation, set the IBE bit to 1. When configured as PCS in master operation or GPO,
set the IBE bit to 1 to reflect the pin state in the corresponding GPDI register. Clear the IBE to 0 to reduce power consumption.
When configured as GPI, set the IBE bit to 1.
0
0
ODE
HYS
SRC
WPE
WPS
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Address: Base + 0x011E and Base + 0x0120
Access: Read / write[4:7, 10:15]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
PA
OBE
1
1
When configured as ETRIG, the OBE bit has no effect. When configured as GPO, set the OBE bit to 1.
IBE
2
2
When configured as ETRIG or GPO, set the IBE bit to 1 to reflect the pin state in the corresponding GPDI register. Clear the
IBE to 0 to reduce power consumption. When configured as GPI, set the IBE bit to 1.
0
0
ODE
HYS
SRC
WPE
WPS
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Summary of Contents for MPC5553
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