Freescale Semiconductor MPC5553, Reference Manual

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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 15-5
system RAM is cached, dirty cache lines may not be completely written to memory unless the region is set
for write through mode.
15.7 Initialization/Application Information
To use the SRAM, the ECC must check all bits that require initialization after power on. A 64-bit
cache-inhibited write to each SRAM location must be used in the application initialization code to
initialize the SRAM array. If the write is not the entire 64 bits wide (8-, 16-, or 32-bits), a read / modify /
write operation is generated that checks the ECC value upon the read. Refer to
Section 15.6, “SRAM ECC
Mechanism .”
NOTE
The SRAM must be initialized, even if the application does not use ECC
reporting.
15.7.1 Example Code
For proper initialization, perform a 64-bit write to all SRAM locations. The Power Architecture embedded
category instruction set provides the store multiple word (
stmw) instruction to implement 64-bit writes.
The stmw instruction concatenates two 32-bit registers for use as a single 64-bit write. To ensure that the
writes are 64 bits, they must be on 64-bit word-aligned boundaries and specify an even number of registers.
The following example code illustrates the use of the stmw instruction to initialize the SRAM ECC bits.
init_L2RAM:
lis r11,0x4000 # base address of the L2SRAM, 64-bit word aligned
ori r11,r11,0 # not needed for this address but could be forothers
li r12,512 # loop counter to get all of L2SRAM;
# 64k/4 bytes/32 GPRs = 512
mtctr r12
init_l2ram_loop:
stmw r0,0(r11) # write all 32 GPRs to L2SRAM
addi r11,r11,128 # inc the ram ptr; 32 GPRs * 4 bytes = 128
bdnz init_l2ram_loop # loop for 64k of L2SRAM
blr # done