Freescale Semiconductor MPC5553, Reference Manual

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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 18-5
18.1.3.1.2 eTPU Timer Channels
Each eTPU engine has 32 identical, independent channels. Each channel corresponds to an input/output
signal pair. Every channel has access to two 24-bit counter registers, TCR1 and TCR2.
Each channel consists of event logic which supports a total of four events, two capture and two match
events. The event logic contains two 24-bit capture registers and two 24-bit match registers. The match
registers are compared to a selected TCR by greater-than-or-equal-to and equal-only comparators. The
match and compare register pairs enable many combinations of single and double-action functions.
The channel configuration can be changed by the microengine. Each channel can perform double capture,
double match or a variety of other capture-match combinations. Service requests may be generated on one
or both of the match events and/or on one of the capture events.
Digital filters that have different filtering modes are provided for the input signals.
Every channel can use any time base or angle counter for either match or capture operation. For example,
a match on TCR1 can capture the value of TCR2. The channels can request service from the microengine
due to recognized pin transitions (input events) or time base matches.
Every eTPU channel may be configured with the following combinations:
• Single input capture, no match (TPU3 functionality)
• Single input capture with single match time-out (TPU3 functionality)
• Single input capture with double match time-out with several double match submodes
• Double input capture with single or double match time-out with several double match submodes
• Single output match (TPU3 functionality)
• Double output match with several double match submodes
• Input-dependent output generation
The double match functionality has various combinations for generation of service request and
determining pin actions.
18.1.3.1.3 Host Interface
The engine’s host interface allows the MPC5553/MPC5554 core to control the operation of the eTPU. In
order for the eTPU to start operation, the MPC5553/MPC5554 core must initialize the eTPU by writing to
the appropriate host interface registers to assign a function and priority to each channel. In addition, the
MPC5553/MPC5554 core writes to the host service request and channel configuration registers to further
define operation for each initialized channel.
NOTE
The host transfers the code image for the eTPU microcode to the SCM, then
the host enables eTPU access to the SCM (which also disables host access).
18.1.3.1.4 Shared Data Memory (SDM)
The SDM works as data RAM that can be accessed by the MPC5553/MPC5554 core and up to two eTPU
engines. This memory is used for either:
• Information transfer between the MPC5553/MPC5554 core and the eTPU
• Data storage for the eTPU microcode program
• Communication between the two eTPU engines
The SDM width is 32 bits, and is accessible by the host in any of the three formats: byte, 16-bit, or 32-bit.
The eTPU can access the SDM’s full 32 bits, lower 24 bits or upper byte (8-bit).