Freescale Semiconductor MPC5553, Reference Manual

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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 14-17
14.3.4.2.6 MII Management Frame Register (MMFR)
The MMFR is accessed by the user and does not reset to a defined value. The MMFR register is used to
communicate with the attached MII compatible PHY devices, providing read/write access to their MII
registers. Performing a write to the MMFR will cause a management frame to be sourced unless the MSCR
has been programmed to 0. In the case of writing to MMFR when MSCR = 0, if the MSCR register is then
written to a non-zero value, an MII frame will be generated with the data previously written to the MMFR.
This allows MMFR and MSCR to be programmed in either order if MSCR is currently zero.
Table 14-9. ECR Field Descriptions
Bits Name Description
0–29 — Reserved.
30 ETHER_EN When this bit is set, the FEC is enabled, and reception and transmission are possible.
When this bit is cleared, reception is immediately stopped and transmission is stopped
after a bad CRC is appended to any currently transmitted frame. The buffer descriptors for
an aborted transmit frame are not updated after clearing this bit. When ETHER_EN is
deasserted, the DMA, buffer descriptor, and FIFO control logic are reset, including the
buffer descriptor and FIFO pointers. The ETHER_EN bit is altered by hardware under the
following conditions:
• ECR[RESET] is set by software, in which case ETHER_EN will be cleared
• An error condition causes the EIR[EBERR] bit to set, in which case ETHER_EN will be
cleared
31 RESET When this bit is set, the equivalent of a hardware reset is performed but it is local to the
FEC. ETHER_EN is cleared and all other FEC registers take their reset values. Also, any
transmission/reception currently in progress is abruptly aborted. This bit is automatically
cleared by hardware during the reset sequence. The reset sequence takes approximately
8 system clock cycles after RESET is written with a 1.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R ST OP PA RA TA
W
Reset U U U U U U U U U U U U U U U U
Address Base + 0x0040
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R DATA
W
Reset U U U U U U U U U U U U U U U U
Address Base + 0x0040
1
“U” signifies a bit that is uninitialized.
Figure 14-8. MII Management Frame Register (MMFR)