Freescale Semiconductor MPC5553, Reference Manual

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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
22-32 Freescale Semiconductor
Soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock
domains. Therefore, it may take some time to fully propagate its effects. The SOFTRST bit remains
asserted while soft reset is pending, so software can poll this bit to know when the reset has completed.
After the module is enabled (CAN x _MCR[MDIS] bit negated), FlexCAN2 should be put into freeze mode
before doing any configuration. In freeze mode, FlexCAN2 is un-synchronized to the CAN bus, the HALT
and FRZ bits in CAN
x _MCR are set, the internal state machines are disabled and the FRZACK and
NOTRDY bits in the CAN x _MCR are set. The CNTX pin is in recessive state and FlexCAN2 does not
initiate frame transmission nor receives any frames from the CAN bus. Note that the message buffer
contents are not affected by reset, so they are not automatically initialized.
For any configuration change/initialization, it is required that FlexCAN2 is put into freeze mode (see
Section 22.4.6.1, “Freeze Mode ). The following is a generic initialization sequence applicable for the
FlexCAN2 module:
• Initialize CANx_CR.
— Determine bit timing parameters: PROPSEG, PSEG1, PSEG2, RJW.
— Determine the bit rate by programming the PRESDIV field.
— Determine internal arbitration mode (LBUF bit).
• Initialize message buffers.
— The control and status word of all message buffers may be written either as active or inactive.
— Other entries in each message buffer should be initialized as required.
• Initialize CANx_RXGMASK, CANx_RX14MASK, and CANx_RX15MASK registers for
acceptance mask as needed.
• Set required mask bits in CAN x _IMRH and CAN x _IMRL registers (for all MBs interrupts), and
in CAN x _CR (for bus off and error interrupts).
• Negate the CAN x _MCR[HALT] bit.
Starting with this last event, FlexCAN2 attempts to synchronize with the CAN bus.
22.5.2 FlexCAN2 Addressing and RAM Size
There are 1024 bytes of RAM for a maximum of 64 message buffers. The user can program the maximum
number of message buffers (MBs) using the MAXMB field in the CAN
x _MCR. For this 1024-byte RAM
configuration, MAXMB can be any number from 0
–
63.