Freescale Semiconductor MPC5553, Reference Manual

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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 10-13
However, the time for the processor to recognize the assertion or negation
of the external input to it is not defined by the book E architecture and can
be greater than 0. Therefore, insert instructions between the reading of the
INTC_IACKR and the setting of MSR[EE] that consume at least two
processor clock cycles. This length of time allows the negation of the
interrupt request to propagate through the processor before MSR[EE] is set.
10.3.1.4 INTC End-of-Interrupt Register (INTC_EOIR)
Writing to the INTC_EOIR signals the end of the servicing of the interrupt request. When the INTC_EOIR
is written, the priority last pushed on the LIFO is popped into INTC_CPR. The values and size of data
written to the INTC_EOIR are ignored. Those values and sizes written to this register neither update the
INTC_EOIR contents or affect whether the LIFO pops. For possible future compatibility, write four bytes
of all 0’s to the INTC_EOIR.
Reading the INTC_EOIR has no effect on the LIFO.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R VTBA (most significant 16 bits)
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reg Addr Base + 0x0010
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R VTBA (least significant 5 bits) INTVEC 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reg Addr Base + 0x0010
Figure 10-10. INTC Interrupt Acknowledge Register (INTC_IACKR)
Table 10-6. INTC_IACKR Field Descriptions
Bits Name Description
0–20 VTBA Vector table base address. Can be the base address of a vector table of addresses of
ISRs. The VTBA only uses the leftmost 20 bits when the VTES bit in INTC_MCR is
asserted.
21–29 INTVEC Interrupt vector. Vector of the peripheral or software settable interrupt request that
caused the interrupt request to the processor. When the interrupt request to the
processor asserts, the INTVEC is updated, whether the INTC is in software or
hardware vector mode.
Note: If INTC_MCR[VTES] = 1, then INTVEC field is shifted left one position to bits
20–28. VTBA is then shortened by one bit to bits 0–19.
30–31 — Reserved.