Freescale Semiconductor MPC5553, Reference Manual

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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
15-6 Freescale Semiconductor
15.8 Revision History
Table 15-3. Changes to MPC5553/5554RM for Rev. 4.0 Release
Description of Change
• Added Modes of Operation section and the subsections Normal Functional Mode, Standby Mode, and Data Retention.
• Replaced Functional Description,
Section 15.5, “Functional Description ” with new wording:
From: The RAM BIU generates a 72-bit code word based upon a 64-bit data write. The ECC scheme will correct all single
bit corrections, and flag all double-bit errors. Some bit errors greater than 2 bits will be flagged as multiple bit errors. The
codeword of 72íb0 and 72íb1 will cause a multi-bit error. Detected multiple bit errors will assert an error indication with
the bus cycle, as well as setting a flag.
To: “The ECC checks are performed during the read portion of an SRAM ECC read/write (R/W) operation, and ECC
calculations are performed during the write portion of a read/write (R/W) operation.
Because the ECC bits can contain random data after the device is powered on, you must initialize the SRAM by
executing 64-bit write instructions to the entire SRAM. For more information, refer to Section 15.7,
“Initialization/Application Information .”
• Revised SRAM ECC Mechanism, Section 15.6.1, “SRAM ECC Mechanism :”
From: The ECC is calculated for each 64-bits of data. For example, for a byte write:
1. The 64-bit word (doubleword-aligned) is read, which causes a check of ECC on all 64-bits. If a correctable error is
detected, it will be corrected prior to merging in the write data. If a non-correctable error occurs during the read portion
of the write operation, then the write will not be performed.
2. The byte data is merged and the ECC is generated for the new 64-bit data value.
3. The data and ECC bits are written back.
In the case of a 64-bit write, the 64-bit word is not read for the merge operation. Instead, the ECC is generated for the
64-bit word data then both data and ECC bits are written. Because the ECC bits will contain random data after power
on, the 64-bit write mechanism is used to initialize the SRAM and insure
To: Internal SRAM write operations are performed on the following byte boundaries:
— 1 byte (0:7 bits)
— 2 bytes (0:15 bits)
— 4 bytes or 1 word (0:31 bits)
— 8 bytes or 2 words (0:63 bits)
If the entire 64 data bits are written to SRAM, no read operation is performed and the ECC is calculated across the entire
64-bits. The ECC bits are then merged with the data segment and written to SRAM.
If the write operation is less than the entire 64-bit data width (1-, 2-, or 4-byte segment), the following occurs:
-- The ECC checks the entire 64-bits for errors. Hardware corrects single-bit errors and flags double-bit errors. Bit errors
greater than 2 bits are flagged as multiple-bit errors.
-- The write data-bytes (1-, 2-, or 4-byte segment) and the ECC bits are merged with the original 64-bit data.
-- The ECC bits are then calculated on the new 64-bit data field.
-- The entire 8-bytes and the new ECC bits are written to SRAM.