Emerson Pm8560 User Manual Download

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Pm8560:

Octal E1/T1/J1 Line Interface PTMC

User’s Manual

from Emerson Network Power

™

Embedded Computing

Octo

ber 2007

Summary of Contents for Pm8560

Page 1: ...Pm8560 Octal E1 T1 J1 Line Interface PTMC User s Manual from Emerson Network Power Embedded Computing October 2007 ...

Page 2: ...ny license under Emerson patents or the rights of others Emerson Consider It Solved is a trademark and Business Critical Continuity Emerson Net work Power and the Emerson Network Power logo are trademarks and service marks of Emerson Electric Co 2007 Emerson Electric Co Copyright 2007 Emerson Electric Co All rights reserved Revision Level Principal Changes Date 10006609 00 Original release March 2...

Page 3: ...nce when the equipment is operated in a commer cial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful inter ference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the ...

Page 4: ...gy Equipment Radio disturbance characteristics Limits and methods of measurement EN55024 1998 Information Technology Equipment Immunity characteristics Limits and methods of measurement EN300386 V 1 3 1 Electromagnetic compatibility and radio spectrum matters ERM Telecommunication network equipment EMC requirements As manufacturer we hereby declare that the product named above has been designed to...

Page 5: ...peed Ethernet Controllers 3 9 Local Bus Controller 3 9 Chip Select Generation 3 9 Processor Reset and Clocking Signals 3 10 MPC8560 Exception Handling 3 10 4 On Card Memory Soldered Flash 4 1 Serial EEPROMs 4 2 Emerson Memory Map 4 2 Double Data Rate SDRAM 4 3 DDR SDRAM Programming 4 3 5 Serial I O Serial Ports 5 1 Serial Port Connector P17 and Cable5 1 Baud Rate Selection 5 2 Baud Rate Generator ...

Page 6: ... 24 Write Recovery Time 8 25 Internal Write to Read Command Delay 8 25 9 Ethernet Interfaces Ethernet Transceiver 9 1 MDIO MDC Signals 9 1 Ethernet Address 9 1 Ethernet Connector 9 2 10Development Mezzanine Card DMC Circuit Board 10 1 Connectors 10 2 P1 Connector Pin Assignments 10 3 P2 EIA 232 Interface 10 5 P3 JTAG COP 10 5 P4 JTAG Chain Header 10 6 DMC Jumpers and LEDs 10 7 DMC Setup 10 8 Insta...

Page 7: ...Test Commands 11 17 diags 11 17 mtest 11 17 um 11 17 test_watchdog 11 17 Other Commands 11 18 autoscr 11 18 base 11 18 bdinfo 11 18 coninfo 11 18 crc32 11 18 date 11 18 echo 11 19 enumpci 11 19 getmonver 11 19 go 11 19 help 11 19 iminfo 11 19 loop 11 19 memmap 11 20 moninit 11 20 mon2init 11 20 monrecovery 11 21 pci 11 21 ping 11 21 reset 11 21 run 11 22 script 11 22 showmac 11 22 showpci 11 22 sl...

Page 8: ...Contents continued Pm8560 User s Manual 10006609 03 vi ...

Page 9: ...Assembly Emerson part number C00003555 xx 5 2 Figure 6 1 Data Flow Between Framer and MPC8560 6 4 Figure 7 1 MPC8560 PCI Controller Block Diagram 7 1 Figure 7 2 PMC Interface Connectors P11 P14 7 6 Figure 8 1 Boot Device Diagram 8 10 Figure 8 2 Clock and Sync Registers Diagram 8 13 Figure 10 1 DMC Component Map Top and Bottom rev 01 10 2 Figure 10 2 P1 PCB To PCB Connector 10 3 Figure 10 3 DMC P2 ...

Page 10: ...Pm8560 User s Manual 10006609 03 viii blank page ...

Page 11: ...2 Connector P14 Pin Assignments 6 6 Table 7 1 Pm8560 Vital Product Data Format 7 2 Table 7 2 Power on Reset Configuration 7 5 Table 7 3 Interrupt Connections for Pm8560 7 6 Table 7 4 P11 P12 and P13 Connector Pin Assignments 7 7 Table 8 1 PLD Register Summary 8 1 Table 9 1 MDIO MDC Signals 9 1 Table 9 2 Ethernet Port Address Numbering 9 2 Table 9 3 Ethernet Port Pin Assignments 9 2 Table 10 1 DMC ...

Page 12: ...Pm8560 User s Manual 10006609 03 x blank page ...

Page 13: ...4 Register 8 16 Framer Clock Source FCSR 0x44 8 14 Register 8 17 MT4095 System Synchronizer Control SSCR 0x48 8 15 Register 8 18 SYNC Source SSR 0x4C 8 16 Register 8 19 Primary Clock Source PCSR 0x50 8 17 Register 8 20 Secondary Clock Source SCSR 0x54 8 18 Register 8 21 TCLK Source TCSR 0x58 8 19 Register 8 22 RCLK Source RCSR 0x5C 8 19 Register 8 23 SPD Row Column SPDRC 0x60 8 20 Register 8 24 SP...

Page 14: ...Pm8560 User s Manual 10006609 03 ii blank page ...

Page 15: ...gion Serial In Out An EIA 232 console serial port from MPC8560 is available at the front panel connector P14 and the DMC or connector P13 when a CT bus is present This port is for boot flash pro gramming and initial setup A second serial port is routed out connector P14 Framer The Pm8560 supports eight links using one IDT82P2288 octal T1 E1 J1 long haul short haul framer and line interface unit LI...

Page 16: ... Manual for more infor mation Transition Model TM TMcSpanP8E provides four or eight rear long or short haul T1 or E1 links See the Emerson TMcSpanP8E User s Manual for more information Development Mezzanine Card An optional Development Mezzanine Card DMC is available for software development The DMC adds access to the 32 pin PLCC ROM flash socket MPC8560 JTAG header CPLD header four LEDs and four ...

Page 17: ...FF0 000016 Information on particular portions of the memory map can be found in later sections of this manual see Table 1 1 8560 CFG ROM RTC Serial EEPROM Serial EEPROM LEDs P12 P13 P14 P11 Development Mezzanine Card DMC Jumpers LEDs 4 COP Header ROM Socket CPLD Header Magnetics 10 100 1000 PHY EIA 232 Serial Reset ETH 1 L N K A C T DMC Connector Logic Reset Control Chip Select Registers Clock Con...

Page 18: ...8 0018 E808 001C E808 0024 E808 0028 SPD Minmum Active to Precharge E808 0020 SPD SDRAM Cycle Time for CAS LAT SPD Minimum Row Precharge SPD Minimum Delay RAS to CAS SPD Minimum Auto Refresh to Active E808 0004 E808 0008 E808 000C E808 0010 E808 0014 E808 002C E808 0030 E808 0034 E808 0038 E808 003C E808 0040 E808 0044 E808 0048 E808 004C E808 0050 E808 0054 E808 0058 E808 005C E808 0060 E808 0064...

Page 19: ...06C R SPD Minimum Row Precharge Time SPDMRP 8 22 E808 0068 R SPD SDRAM Cycle Time for CAS LAT SPDCT 8 21 E808 0064 R W SPD Channel Associated Signaling CAS Latency LAT Refresh SPDCLR 8 21 E808 0060 R W SPD Row Column SPDRC 8 20 E808 005C R W RCLK Source RCSR 8 19 E808 0058 R W TCLK Source TCSR 8 19 E808 0054 R W Secondary Clock Source SCSR 8 18 E808 0050 R W Primary Clock Source PCSR 8 17 E808 004...

Page 20: ...Agency Compliance E808 0014 R Hardware Configuration 1 HCR1 8 4 E808 0010 reserved E808 000C R W Phase locked Loop Configuration PLLCR 8 3 E808 0008 R PLD Version PVR 8 3 E808 0004 R Hardware Version HVR 8 2 E808 00001 R Product Identification PIDR 8 2 E800 8000 reserved E800 0000 R W IDT82P228x SCT 4 KB E200 0000 reserved E000 0000 R W Soldered Flash 32 MB 4 1 A100 0000 reserved A000 0000 R W PCI...

Page 21: ... use of six substances cadmium Cd mercury Hg hexava lent chromium Cr VI polybrominated biphenyls PBBs polybrominated diphenyl ethers PBDEs and lead Pb Configurations that are RoHS compliant are built with lead free sol der To obtain a certificate of conformity CoC for the Pm8560 send an e mail to sales arte syncp com or call 1 800 356 9602 Have the part number e g C0001234 xx for your configuratio...

Page 22: ...7 2004 MPC8560 Integrated Processor Hardware Specifications Freescale Semiconductor Inc MPC8450EC Rev 3 1 12 2004 Migrating from PowerQUICC II to PowerQUICC III Application Note Freescale Semiconductor Inc AN2662 Rev 0 05 2004 http www freescale com EEPROM Atmel Two Wire Serial EEPROM 32K 4096x8 64K 8192x8 Atmel 3054O SEEPR 1 05 http www atmel com literature Ethernet 88E1111 Data Sheet Integrated ...

Page 23: ... 3 4 http www altera com PMC IEEE Standard for a Common Mezzanine Card Family CMC IEEE Std 1386 2001 IEEE New York NY IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC IEEE Std 1386 1 2001 IEEE New York NY http www ieee org American National Standard for Processor PMC ANSI VITA 32 2003 Approved July 2003 http www vita com SDRAM 512Mb x4 x8 x16 Double Data Rate DDR SDRAM M...

Page 24: ...Module Emerson TMcSpanP8E User s Manual Emerson Network Power 10005363 xx http www emersonembeddedcomputing com 1 Frequently the most current information regarding addenda errata for specific documents may be found on the corresponding web site Device Interface Document 1 continued ...

Page 25: ...r static protection and handle Pm8560 boards only when absolutely necessary Always wear a wriststrap to ground your body before touching a board Keep your body grounded while handling the board Hold the board by its edges do not touch any components or circuits When the board is not in an enclosure store it in a static shielding bag To ground yourself wear a grounding wriststrap Simply placing the...

Page 26: ... R21 C59 C64 R25 R32 R24 C75 C71 R34 R36 R37 R33 R38 R1 R2 R3 R4 R40 R41 R47 R44 R43 R42 C82 C84 C101 R46 R45 C96 C98 R50 R49 R48 R51 R52 R53 R54 C100 R57 R56 R55 RN10 RN7 RN6 RN11 RN9 U13 U12 U5 IDT82P2288 QUAD Framer U14 U2 RN33 RN32 RN30 RN34 RN31 U1 Transformer RN5 RN3 RN35 R39 RN1 RN2 RN4 RN26 RN24 RN20 RN22 RN28 RN18 RN16 RN12 RN14 RN27 RN25 RN21 RN23 RN29 RN19 RN17 RN13 RN15 RN8 R11 R12 CR3...

Page 27: ...R246 R245 R241 R242 C315 R223 R224 R236 R235 R253 R252 R251 R258 R259 R260 R254 R255 R256 R257 R261 R262 R263 R264 R175 R176 R177 R178 R180 R181 R182 R183 R184 R185 R186 R81 R179 R198 C253 C258 R199 C262 R200 R188 R189 R191 R197 C263 R187 R250 R202 R145 R144 C252 C250 C156 C157 C152 C164 C176 C151 C165 C153 C167 C171 C194 C185 C192 C193 C186 C195 C196 C188 C175 C187 C155 C150 C154 C166 C181 C191 C...

Page 28: ... 2 4 Figure 2 3 LED and Switch Locations Top CR16 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR5 CR6 FL0_LED FL1_LED SKT_LED DEBUG_LED4 DEBUG_LED3 DEBUG_LED2 DEBUG_LED1 CPU_CKSTP_OUT CPU_REDLED CPU_GREENLED Boot Device Debug CPU FP_SIO_LED P13_SIO_LED Serial IO ...

Page 29: ...ble with Emerson s custom Development Mezzanine Card DMC allows field programming for the Pm8560 See page 10 3 for DMC P1 pin assignments Front Panel The single width Pm8560 front panel includes an Electromagnetic Interference EMI gas ket See Fig 1 1 for the connector reset switch and LED locations The electromagnetic compatibility EMC tests used a Pm8560 model that includes a front panel assembly...

Page 30: ...pport html on the internet or send E mail to support artesyncp com Environmental Considerations As with any printed circuit board be sure that air flow to the board is adequate Chassis con straints and other factors greatly affect the air flow rate The environmental requirements are as follows Table 2 2 Environmental Requirements Reset Methods Several reset sources are available on the Pm8560 Soft...

Page 31: ...he device CPLD or use an In circuit Emulator ICE debugger in conjunc tion with the MPC8560 COP JTAG port Refer to pages 10 5 and 10 6 for detailed views of the DMC debug connectors Flash COP JTAG Header Framer MT9045 GB Ethernet Voltage Monitor 250mS Delay Voltage Monitor 250mS Delay P11 P12 MPC8560 Processor CPU_HRESET CPU_SRESET CPU_TRST HRESET_REQ WDE CPU RESET CONFIG REGISTER ACCESS FLASH_RST ...

Page 32: ...connectors and the keying holes with the PMC connectors J11 through J14 and the keying pin on the baseboard Press the module into place making sure that the connectors are firmly mated and the module front panel is fully seated in the baseboard front panel Caution Avoid damaging the front panel EMC gasket Framer MT9045 GB Ethernet P11 P12 MPC8560 Processor TD DMC COP JTAG Header CPLD ISP Header De...

Page 33: ...ase of difficulty use this checklist Be sure the Pm8560 circuit board is seated firmly on the baseboard and the baseboard is seated in the carrier Be sure the system is not overheating Check the cables and connectors to be certain they are secure Check your power supply for proper DC voltages If possible use an oscilloscope to look for excessive power supply ripple or noise over 50 mVpp below 10 M...

Page 34: ...ee Fig 11 1 for location baseboard serial number product ID and monitor version if applicable RTM serial number and product ID version and part number of the operating system if applicable whether your board has been customized for options such as a higher processor speed or additional memory license agreements if applicable If you do not have internet access call Emerson for further assistance 80...

Page 35: ...r plus your purchase order number and billing information if your Pm8560 hardware is out of warranty Contact our Test and Repair Services Department for any war ranty questions If you return the board be sure to enclose it in an antistatic bag such as the one in which it was originally shipped Send it prepaid to Emerson Network Power Embedded Computing Test and Repair Services Department 8310 Exce...

Page 36: ...Setup Troubleshooting Pm8560 User s Manual 10006609 03 2 12 ...

Page 37: ...apable of issuing and completing two instructions per clock cycle 7 pipeline stages Auxiliary Processing Units APUs page address translation core registers L1 Cache 32 kilobyte data and 32 kilobyte instruction cache 32 byte line eight way set associative parity protection L2 Cache 256 kilobyte on chip CPU Core Speed 800 MHz Communication Processor Module CPM RISC CPM four Serial Communications Con...

Page 38: ...MPC8560 FUNCTIONS The MPC8560 provides the following functions on the Pm8560 module System functions include DDR SDRAM memory controller Chip select generation for the framers and PLD General purpose I O GPIO DMA capability I2 C controller The MPC8560 has two physical serial DMA SDMA channels The CPM implements two dedicated virtual SDMA channels and two virtual SDMA channels for each FCC MCC SCC ...

Page 39: ...r sets as listed in the following priority Machine Check highest priority Machine Check Save and Restore registers MCSRR0 MCSRR1 save state when they are taken and use rfmci instruction to restore state The machine check enable bit MSR ME can mask these interrupts Noncritical The processor is able to change program flow to handle conditions generated by external signals errors or unusual condition...

Page 40: ...t Controller The CPM interrupt controller receives interrupts from internal sources for example FCCs SCCs or timers and from external pins port C 0 15 as shown in Fig 3 1 The internal interrupt sources may each be assigned to a particular interrupt level in software Interrupt levels may be programmed for logic low or negative edge assertion The interrupt controller combines all the sources into a ...

Page 41: ... IRQ3 PMC_PCI_INTC AA21 IRQ4 PMC_PCI_INTB Y19 IRQ5 PMC_PCI_INTA AA19 IRQ6 IRQ7_PU AG25 reserved IRQ8_PU AB20 reserved IRQ9_PU Y20 reserved IRQ10_PU AF26 reserved IRQ11_PU AH24 reserved SS_FASTLOCK PC5 MT9045 system synchronizer fast lock mode SS_PPC PC6 MT9045 system synchronizer phase continuity control SS_TCLR PC7 MT9045 system synchronizer time interval error TIE circuit reset SS_LOCK PC8 MT904...

Page 42: ... synchronization PA7 TDM1_TSYNC in TDM port 1 transmit synchronization PA8 TDM1_RXD in TDM port 1 receive data PA9 TDM1_TXD out TDM port 1 transmit data PA10 reserved PA11 reserved PA12 reserved PA13 reserved PA14 reserved PA15 reserved PA16 FCC1_RXD1 in receive data 1 PA17 FCC1_RXD0 in receive data 0 PA18 FCC1_TXD0 out transmit data 0 PA19 FCC1_TXD1 out transmit data 1 PA20 reserved PA21 reserved...

Page 43: ...n TDM port 8 receive synchronization PB21 TDM8_TSYNC in TDM port 8 transmit synchronization PB22 TDM8_RXD in TDM port 8 receive data PB23 TDM8_TXD out TDM port 8 transmit data PB24 TDM7_RSYNC in TDM port 7 receive synchronization PB25 TDM7_TSYNC in TDM port 7 transmit synchronization PB26 TDM7_RXD in TDM port 7 receive data PB27 TDM7_TXD out TDM port 7 transmit data PB28 TDM6_TSYNC in TDM port 6 t...

Page 44: ...TDM4_TCLK in TDM port 4 transmit clock 8 PC25 TDM4_RCLK in TDM port 4 receive clock 7 PC26 TDM3_TCLK in TDM port 3 transmit clock 6 PC27 TDM3_RCLK in TDM port 3 receive clock 5 PC28 TDM2_TCLK in TDM port 2 transmit clock 4 PC29 TDM2_RCLK in TDM port 2 receive clock 3 PC30 TDM1_TCLK in TDM port 1 transmit clock 2 PC31 TDM1_RCLK in TDM port 1 receive clock 1 PD4 DMC_LED4 out Development mezzanine ca...

Page 45: ...rogrammable Machine UPM interfaces synchronous devices The Synchronous DRAM SDRAM controller provides access to standard SDRAM Chip Select Generation The MPC8560 memory controller functions as a chip select CS generator to access on board memory devices saving the board s area which results in reduced cost power con sumption and increased flexibility Table 3 4 lists the chip selects for the Pm8560...

Page 46: ...eset operation and is not in a power down nap doze or sleep or debug state SYS_CLK System Clock is the primary clock input to the e500 core and all the devices and interfaces that operate synchronously with the core RTC Real Time Clock is an input to the MPC8560 Optionally it can be used to clock the e500 core timer facilities and by the MPC8560 PIC global timer facilities MPC8560 Exception Handli...

Page 47: ...ks are selectively and individually lockable and unlockable in system A 128 bit protection reg ister has multiple uses including unique flash device identification Before programming or erasing a block in flash mask the internal reset sources for HRESET so that the board does not allow reset until flash is programmed or erased See page 11 4 for updating the moni tor in soldered flash A block erase...

Page 48: ...oth trans mit and receive operations Initialization software for the I2 C EEPROM should issue a start condition immediately followed by a stop condition to reset EEPROM to a known state since the chip maintains its state even between power ups For more information on the Atmel EEPROM refer to the Atmel Two wire Serial EEPROM 32K 4096x8 64K 8192x8 Emerson Memory Map The Pm8560 uses a 64 kilobyte I2...

Page 49: ...rror correct ing Code ECC by detecting and correcting all single bit errors and detects all double bit errors and all errors within a nibble Figure 4 1 MPC8560 To SDRAM Connection DDR SDRAM Programming After power up the DDR SDRAM must be initialized by issuing a Mode register set com mand to establish its mode of operation During that command execution data is read by the Mode register from the S...

Page 50: ...9 03 4 4 A12 A7 12 7 Operating Mode 000000 Normal operation A6 A4 6 4 CAS Latency 010 Data valid two cycles after CAS asserted A3 3 Burst Type 0 Sequential burst A2 A0 2 0 Burst Length 010 Four word burst length Address Bus bits Mode Field Value Description continued ...

Page 51: ...ments are shown in Table 6 2 Serial lines consist of serial data in and serial data out for each port only The ports do not include handshaking A transceiver translates the serial lines to EIA 232 This provides Operation from a single 3 3 volt supply Two drivers and two receivers in one package Over 10 kilovolt ESD protection Operating up to 120 kilobaud Auto shutdown automatically enters a low po...

Page 52: ... baud rate generator may be routed to mul tiple FCCs or SCCs Anexternal Voltage ControllerOscillator VCO provides the input frequencyfor the internal MPC8560 baud rate generators This frequency is divided down to generate the console port frequencies The baud rate is calculated from the PCI clock SysCLK optimal speeds include 33 MHz and 66 MHz Table 5 3 lists the clock divider values associated wi...

Page 53: ...F9 15F016 and BRGC1 4 regis ters start at physical address space FDF9 19F016 For more detailed information on these registers refer to the MPC8560 PowerQuicc III Integrated Communications Processor Reference Manual BRG Clock Divider Value Baud Rate 1 1 The EIA 232C specification defines a maximum rate of 20 000 bits per second over a typical 50 foot cable 2 500 picofarads maximum load capacitance ...

Page 54: ...Serial I O Baud Rate Selection Pm8560 User s Manual 10006609 03 5 4 ...

Page 55: ... INTERFACE The Pm8560 module includes support for eight links using one IDT82P2288 octal T1 E1 J1 long haul short haul framer and line interface LIU Framer Each link can be configured as T1 E1 or J1 Frame alignment generation for T1 per ITU T G 704 TA TSY 000278 TR TSY 000008 E1 per ITU T G 704 J1 per JT G 704 and unframed mode Signaling extraction insertion for CAS and RBS signaling Each link has...

Page 56: ...ce uses the clock and sync registers starting on page 8 12 for system configu ration Specific configurations also use the MT9045 System Synchronizer device Setting up the MT9045 in the desired mode and frequency requires two steps 1 Drive the correct Pm8560 CPM port pins PC5 PC6 PC7 PC12 PC13 as defined in Table 3 3 2 Set the appropriate registers in the MT9045 System Synchronizer Control register...

Page 57: ...the MT9045 is not installed PRI clock is used for TCLK and RCLK since PRI clock is the basis of SYNC pulses RSYNC TSYNC Use CT_FA or CT_FB as TSYNC but must use same CT8A or CT8B pair CT8A for TCLK RCLK and CTFA for TSYNC RSYNC or CT8B for TCLK RCLK and CTFB for TSYNC RSYNC If using the on board framer CLK2 048 for TCLK and RCLK then use PRI divide by eight for TSYNC and RSYNC Line rate equal to s...

Page 58: ...ight links REFB Reference clock output B When no LOS is detected this pin outputs a recovered clock from the clock and data recovery functions block of one of the eight links RSCK Receive Side System Clock links 1 8 In receive clock master mode the RSCKn pins out put a 1 544 MHz T1 J1 2 048 MHz E1 clock In receive clock slave mode the RSCKn pins input a 1 544 MHz T1 J1 only 2 048 or 4 096 MHz cloc...

Page 59: ... 3 section User Programmable Arbitrary Waveform It consists of loading values to describe the wave form into the framer RAM and a scale value into a chip register This procedure is repeated for each of the ports being used The data sheet defines the values to load into RAM as a series of tables numbered from 62 to 73 Which table and scale value to use is dic tated by the mode T1 or E1 and the Rear...

Page 60: ... Assignments P14 Pin Signal P14 Pin Signal 1 SIOPORT1_RX_P14 2 no connect 3 SIOPORT1_TX_P14 4 no connect 5 no connect 6 no connect 7 GND 8 SIOPORT2_RX_P14 9 no connect 10 SIOPORT2_TX_P14 11 no connect 12 GND 13 no connect 14 GND 15 TTIP2 16 TRING2 17 no connect 18 RTIP2 19 RRING2 20 TTIP1 21 TRING1 22 no connect 23 RTIP1 24 RRING1 25 no connect 26 3_3V_TO_RTM 27 TM_ID1 28 3_3V_TO_RTM 29 no connect...

Page 61: ...TDM Interface Rear Panel I O Connector P14 10006609 03 Pm8560 User s Manual 6 7 63 RTIP8 64 RRING8 P14 Pin Signal P14 Pin Signal continued ...

Page 62: ...TDM Interface Rear Panel I O Connector P14 Pm8560 User s Manual 10006609 03 6 8 ...

Page 63: ...N switch fabric For more detailed information refer to the MPC8560 PowerQuicc III Integrated Communications Processor Refer ence Manual MPC8560 PCI FEATURES PCI Support 32 and 64 bit interface 66 and 33 MHz 64 bit dual address cycle DAC Address and data parity with error checking and reporting Access to all PCI memory and I O address spaces PCI configuration registers PCI 3 3 volt compatible Compl...

Page 64: ... DID Device Identification 0x0009 VITAL PRODUCT DATA VPD The System Management Bus SMB serial EEPROM contains the Vital Product Data that conforms to PCI Specification 2 2 The SMB provides access to connector P11 from the MPC8560 The monitor supports the VPD capabilities by supplying the following read only data product name Pm8560 product ID number and board serial number Table 7 1 Pm8560 Vital P...

Page 65: ... 00 00 00 00 00 00 00 00 00 00 00 00 78 Note Although monitor version 1 4 does not print it is stored at 0x90 31 2e 34 0F 4E 15 78 64 Manufacturer ID in ASCII Emerson Network Power Embedded Computing 4F 50 79 80 2 Read only part number keyword PN 51 81 1 Length of part number data field 0x0B 11d 52 5C 82 92 11 Part shippable number in ASCII C000XXXX YY 5D 5E 93 94 2 Read only serial number keyword...

Page 66: ...I CONFIGURATION REGISTERS The PCI Local Bus Specification defines the configuration registers within the PCI configura tion header 0x00 through 0x3F The following register map lists the common PCI configu ration header as implemented by the MPC8560 Register 7 2 MPC8560 PCI Configuration Space Header Address Offset hex 31 16 15 0 00 Device ID Vendor ID 04 PCI Bus Status PCI Bus Command 08 Bus Base ...

Page 67: ...cted to the CPLD and is read through the CPLD PCI Status register see PCI Status register 2C Subsystem Device ID Subsystem Vendor ID 30 reserved 34 reserved PCI Bus Capability Pointer 38 reserved 3C PCI Bus MAX_LAT PCI Bus MIN_GNT PCI Bus Interrupt Pin PCI Bus Interrupt Line 40 reserved 44 PCI Bus Arbiter Configuration PCI Bus Function 48 E0 reserved E4 reserved CompactPCI Hot Swap Control and Sta...

Page 68: ...perating in monarch mode these pins should be configured to generate interrupts to the MPC8560 PCI INTERRUPTS Interrupt sources are classified as originating from normal device operation or conditions generated from an exception Interrupt sources associated with normal device operations are listed in Table 7 3 Table 7 3 Interrupt Connections for Pm8560 See page 3 10 for a description of the MPC856...

Page 69: ...o connect JTAG_TRST GND 3 GND JTAG_TMS GND 4 INTA JTAG_QS_TDO P13_STX 5 INTB JTAG_FRM_TDI FCC1_MDC 6 INTC GND P13_SRX 7 PRESENT GND GND FCC1_RXER 8 5 V no connect GND 9 INTD no connect no connect 10 PCI reserved no connect FCC1_TXD0 11 GND no connect no connect 12 PCI reserved 3 3 V FCC1_TXD1 13 CLK RST FCC1_REFCLK 14 GND no connect GND 15 GND 3 3 V GND 16 GNT no connect FCC1_RXD0 17 REQ no connec...

Page 70: ... state signal indicates when a device on the bus has been selected as the target of the current transaction EREADY ENUMERATION READY indicates a non monarch PMC is ready to respond to PCI bus enu meration See the PCI EREADY bit in PCI Status PSR 0x2C FRAME CYCLE FRAME tri state line is driven by the current master to indicate the beginning of an access and continues to be asserted until transactio...

Page 71: ... clock after the completion of the current data phase PERR PARITY ERROR reports parity errors during all PCI transactions tri state REQ BUS REQUEST indicates to the arbiter that a particular master wants to use the bus out put RST RESET assertion brings PCI registers sequencers and signals to a consistent state input SERR SYSTEMS ERROR an open drain signal indicates address parity errors STOP STOP...

Page 72: ...PCI Bus Interface PMC Connector Pin Assignments Pm8560 User s Manual 10006609 03 7 10 ...

Page 73: ...e Register Number 0x00 PIDR Product ID 8 1 0x04 HVR Hardware Version 8 2 0x08 PVR PLD Version 8 3 0x0C PLLCR PLL Configuration 8 4 0x10 reserved 0x14 HCR1 Hardware Configuration 1 8 5 0x18 JSR Jumper Setting 8 6 0x1C LEDR LED 8 7 0x20 RER Reset Event 8 8 0x24 RCR Reset Command 8 9 0x28 PROE PCI Reset Out Enable 8 10 0x2C PSR PCI Status 8 11 0x30 BDFM Boot Device Failover Mechanism 8 12 0x34 MISC M...

Page 74: ... This is hard coded in the PLD and changes with every major PCB artwork version Version starts at 0016 0x68 SPDCT SPD SDRAM Cycle Time for CAS LAT 8 25 0x6C SPDMRP SPD Minimum Row Precharge Time 8 26 0x70 SPDMDBRA SPD Minimum Row Delay Between Activations 8 27 0x74 SPDMDBRCA SPD Minimum Row Delay Between RAS to CAS Assertions 8 28 0x78 SPDMAP SPD Minimum Active to Precharge 8 29 0x7C SPDMAA SPD Mi...

Page 75: ... values are restored when the board is power cycled has a front panel reset or receives a PCI reset that was not the result of the MPC8560 software initiating a PCI RSTOUT command The normal mechanism for changing the PLL frequencies are 1 Baseboard writes the MPC8560 PLLCR via PCI 2 Baseboard writes the MPC8560 PROE register via PCI to mask SW HRESET from causing a PMC RSTOUT 3 Baseboard writes t...

Page 76: ...fic hardware con figurations such as the MT904x clock and DDR memory Register 8 5 Hardware Configuration 1 HCR1 0x14 reserved Default is 00 BDFE Boot Device Failover Enabled see register 8 12 0 BDF disabled 1 BDF enabled default MTSSP MT9045 System Synchronizer clock Present 0 MT9045 not present 1 MT9045 present ECCP Error correcting Code ECC Present 0 ECC is not present 1 ECC is present DDR1 0 DD...

Page 77: ...oots from the DMC socket when a shunt is installed on jumper JP2 3 4 and boots from soldered flash when the shunt is out see Fig 8 1 0 Enables soldered flash default 1 Enables DMC socketed flash DMCPD DMC Presence Detect 0 DMC not installed 1 DMC present TMID3 0 Transition Module Identification The four TMID bits indicate to software which TM is installed 0101 The Emerson TMcSpanP8E is installed 1...

Page 78: ... event which caused a reset When power is first applied the FP_PSH_BUTTN reset event is not latched in the Reset Event register this is the Power on Reset POR event Front panel reset events which occur after power up will be latched Register 8 8 Reset Event RER 0x20 SWPR Software PCI RESETOUT Set to 1 when a PCI RESETOUT has occurred SWHR Software Hard Reset Set to 1 when the last reset was caused...

Page 79: ... 8 9 Reset Command RCR 0x24 CPUHR CPU Hard Reset A CPU hard reset also causes resets to the framer MT9045 flash GbE and PMC reset out when PROE bit 6 is set 0 No reset default 1 Reset FRMR Framer Reset 0 No reset default 1 Reset MTSSR MT9045 System Synchronizer Reset 0 No reset default 1 Reset PMCRO PMC Reset Out This bit allows software to reset the Pm8560 based on the values set in PROE bits 5 0...

Page 80: ...TOUT 0 Disable 1 Enable default SWHR Software Hard Reset 0 Disable 1 Enable default WDE Watchdog Expired 0 Disable 1 Enable default reserved Default is 0 COPH COP Hardware reset 0 Disable 1 Enable FPPB Front Panel Push Button reset POR_RST 0 Disable 1 Enable PCI Status The Pm8560 provides a register for status and control of enumeration and monarch status In a Monarch system the PCIE field is read...

Page 81: ... device The mecha nism relies on the processor s internal watchdog to expire when corrupted code fails to reset the timer To detect corruption before the boot code has configured the internal watchdog a second timer is implemented in the CPLD hardware This CPLD watchdog begins counting down as soon as the board is power cycled or reset If the timer expires approximately half of a second the boot f...

Page 82: ... is 00 BSJ Boot Socket Jumper see register map 8 6 When this shunt JP2 3 4 is installed the BDFM is disabled and the processor boots from the socket 0 Uses BDFM 1 The DMC is installed and the boot from socket shunt JP2 is installed BDS Boot Device is Socket when shunt is installed on DMC jumper JP2 3 4 1 Active boot device is socketed flash 7 6 5 4 3 2 1 0 BF reserved BSJ reserved BDS BDF1 BDF0 In...

Page 83: ...3 choice the hardware can be enabled to combine the received data from both ports Register 8 13 Miscellaneous Control MISC 0x34 REFCLK REFCLK control selects whether the FCC REFCLK is received from the baseboard and subse quently driven to the MPC8560 or if the FCC REFCLK is sourced by the CPLD as a 50 MHz output and also driven to the MPC8560 0 REFCLK input default 1 REFCLK output SROM1 SROM1 wri...

Page 84: ... and connector P13 SIO connec tions Register 8 14 CT Bus Status CTSR 0x38 reserved Default is 000000 PTEN Signal PTENB on connector P13 pin 39 read only 0 PTENB inactive 1 PTENB active default on reset CTEN CT bus connection read write 0 CT bus isolated 1 CT bus connected CLOCK AND SYNC REGISTERS Fig 8 2 is a detailed diagram of the clock and sync registers 0x40 through 0x5c This dia gram is a too...

Page 85: ...LK6 RCLK7 RCLK8 SS_CLK2_048 SS_CLK1_544 SECONDARY_MUX RCLK_MUX RCSR 0 RCSR 1 TCLK_MUX RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 RCLK8 TCLK1 TCLK2 TCLK3 TCLK4 TCLK5 TCLK6 TCLK7 TCLK8 SSR 6 TSYNC1 TSYNC2 TSYNC3 TSYNC4 TSYNC5 TSYNC6 TSYNC7 TSYNC8 RSYNC1 RSYNC2 RSYNC3 RSYNC4 RSYNC5 RSYNC6 RSYNC7 RSYNC8 SYNC_MUX_STRETCHED PRIMARY_MUX_DIV_TO_8KHz CT_FB SS_FRMP8KHz CT_FA 8KHz CLOCK RSYNC_IN_MUX Creates S...

Page 86: ...NETREF2 Mode 1 and 0 00 Disable 01 REFA 10 REFB 11 Reserved Framer Clock Source Register 8 16 Framer Clock Source FCSR 0x44 reserved Default is 000 CTC8B CT bus C8B 8 192 MHz clock 0 Disable 1 Enable CTC8A CT bus C8A 8 192 MHz clock 0 Disable 1 Enable MT1 5 MT9045 1 544 MHz clock 0 Disable 1 Enabled MT2 0 MT9045 2 048 MHz clock 0 Disable 1 Enable 7 6 5 4 3 2 1 0 reserved N1M1 N1M0 N2M1 N2M0 7 6 5 ...

Page 87: ...puts to the MT9045 and indicate what frequency is present on its primary or secondary inputs 00 19 44 MHz 01 8 kHz 10 1 544 MHz T1 11 2 048 MHz E1 Note FS1 and FS2 read the state of the signals driven by the CPLD to the MT9045 inputs To change the state of the FSx pins write to the RSCR bit 7 SSLOCK System Synchronizer filtered version of LOCK pin read only See Table 3 2 for the unfiltered version...

Page 88: ...elects the SEC reference source SYNC Source Register 8 18 SYNC Source SSR 0x4C TSYNCE TSYNC Enable 0 Tristate 1 Drive TSYNC RSYNCE RSYNC Enable 0 Tristate 1 Drive RSYNC RSYNC RSYNC 0 Disable 1 Enable CTFA CT_FA 0 Disable 1 Enable CTFB CT_FB 0 Disable 1 Enable MT8K MT4095 8 KHz clock 0 Disable 1 Enable PRIM8K Primary MUX divide to 8 KHz 0 Disable 1 Enable reserved Default is 0 7 6 5 4 3 2 1 0 TSYNC...

Page 89: ...EL0 RCLK Select 2 0 000 TDM1 selected 001 TDM2 selected 010 TDM3 selected 011 TDM4 selected 100 TDM5 selected 101 TDM6 selected 110 TDM7 selected 111 TDM8 selected RCLK RCLK 0 Disable 1 Enable FR1 5 Framer 1 544 MHz clock 0 Disable 1 Enable FR2 0 Framer 2 048 MHz clock 0 Disable 1 Enable CTC8A CT bus C8A 2 048 MHz clock 0 Disable 1 Enable CTC8B CT bus C8B 2 048 MHz clock 0 Disable 1 Enable 7 6 5 4...

Page 90: ...RSEL0 RCLK Select 2 0 000 TDM1 selected 001 TDM2 selected 010 TDM3 selected 011 TDM4 selected 100 TDM5 selected 101 TDM6 selected 110 TDM7 selected 111 TDM8 selected RCLK RCLK 0 Disable 1 Enable FR1 5 Framer 1 544 MHz clock 0 Disable 1 Enable FR2 0 Framer 2 048 MHz clock 0 Disable 1 Enable CTC8A CT bus C8A 2 048 MHz clock 0 Disable 1 Enable CTC8B CT bus C8B 2 048 MHz clock 0 Disable 1 Enable 7 6 5...

Page 91: ...selected 100 TDM5 selected 101 TDM6 selected 110 TDM7 selected 111 TDM8 selected RCLK RCLK 0 Disable 1 Enable MT1 5 MT9045 1 544 MHz clock 0 Disable 1 Enable MT2 0 MT9045 2 048 MHz clock 0 Disable 1 Enable PRIM Primary MUX 0 Disable 1 Enable SECM Secondary MUX 0 Disable 1 Enable RCLK Source Register 8 22 RCLK Source RCSR 0x5C 7 6 5 4 3 2 1 0 RSEL2 RSEL1 RSEL0 RCLK MT1 5 MT2 0 PRIM SECM 7 6 5 4 3 2...

Page 92: ...ontrol 0 RCLK input PLD receives RCLK 1 RCLK output PLD drives RCLK SERIAL PRESENCE DETECT SPD REGISTERS Row Column Register 8 23 SPD Row Column SPDRC 0x60 RADDR Row Addressing of the on board DDR SDRAM 00 12 row bits 01 13 row bits 10 14 row bits 11 Reserved CADDR Column Addressing of the on board DDR SDRAM 000 8 column bits 001 9 column bits 010 10 column bits 011 11 column bits 100 111 Reserved...

Page 93: ...ck 010 1 5 clocks 011 2 clocks 100 2 5 clocks 101 3 clocks 110 3 5 clocks 111 4 clocks ECC ECC error correction capable for the on board DDR SDRAM 0 Not ECC capable 1 ECC capable SELFR Self Refresh flag for the on board DDR SDRAM 0 Not self refresh capable 1 Self refresh capable REFRATE Refresh Rate for the on board DDR SDRAM 000 Reserved 001 3 9 msec refresh period 010 111 Reserved SDRAM Cycle Ti...

Page 94: ...mum cycle time for the CAS latency speci fied for the on board DDR SDRAM tenth of nanosecond 0000 0 ns 0001 1 ns 0010 2 ns 1000 8 ns 1111 9 ns Minimum Row Precharge Time Register 8 26 SPD Minimum Row Precharge Time SPDMRP 0x6C TRPWHNS Minimum Row Precharge Time for the on board DDR SDRAM whole nanosecond granular ity 000000 Reserved 000001 1 ns 000010 2 ns 000011 3 ns 111110 62 ns 111111 63 ns TRP...

Page 95: ...110 62 ns 111111 63 ns TRPQTRNS Minimum delay between different row activations for the on board DDR SDRAM quarter nanosecond granularity 00 0 ns 01 25 ns 10 50 ns 11 75 ns Minimum Row Delay Between RAS to CAS Assertions Register 8 28 SPD Minimum Row Delay Between RAS to CAS Assertions SPDMDBRCA 0x74 TRCDWHNS Minimum delay required between assertions of RAS and CAS for the on board DDR SDRAM whole...

Page 96: ...Precharge time for the on board DDR SDRAM 00000000 0x00 Reserved 00000001 0x01 1 ns 00000010 0x02 2 ns 00000011 0x03 3 ns 01111111 0x7F 127 ns 10000000 0x80 128 ns 11111110 0xFE 254 ns 11111111 0xFF 255 ns Minimum Auto Refresh to Active Auto Refresh Register 8 30 SPD Minimum Auto Refresh to Active Auto Refresh SPDMAA 0x7C MARTAR Minimum Auto Refresh To Active Auto Refresh command period for the on...

Page 97: ... Reserved 000001 1 ns 000010 2 ns 000011 3 ns 111110 62 ns 111111 63 ns WRTQTRNS Write Recovery Time for the on board DDR SDRAM quarter nanosecond granularity 00 0 ns 01 25 ns 10 50 ns 11 75 ns Internal Write to Read Command Delay Register 8 32 SPD Internal Write to Read Command Delay SPDIWR 0x84 WTRWHNS Internal Write to Read command delay for the on board DDR SDRAM whole nanosecond granularity 0...

Page 98: ...erial Presence Detect SPD Pm8560 User s Manual 10006609 03 8 26 111110 62 ns 111111 63 ns WRTQTRNS Internal Write to Read command delay for the on board DDR SDRAM quarter nanosecond granularity 00 0 ns 01 25 ns 10 50 ns 11 75 ns ...

Page 99: ...nual Refer to the Marvell web site at http www marvell com MDIO MDC Signals Table 9 1 identifies the Marvell 88E1111 Ethernet and MPC8560 processor Management Data Input Output MDIO and Management Data Clock MDC signals Table 9 1 MDIO MDC Signals ETHERNET ADDRESS The Ethernet address for your board is a unique identifier on a network and must not be altered The address consists of 48 bits MAC 47 0...

Page 100: ...0 is 1032 the calcu lated value is 32 2016 and the port addresses are port 0 Ethernet address is 00 80 F9 59 00 20 port 1 Ethernet address is 00 80 F9 59 80 20 ETHERNET CONNECTOR An RJ45 connector P20 provides the Ethernet debug port access through the front panel see Fig 1 1 The manufacturer part number for this connector is AMP TYCO 1116062 1 Table 9 3 Ethernet Port Pin Assignments Offset MAC De...

Page 101: ...pment by providing access to Four LEDs for software development connected to MPC8560 A JTAG COP debug header for the CPU for example using a CPU debugger A JTAG PLD programming header A 32 pin PLCC 8 bit ROM socket to reload the Monitor since there is not a socket on the Pm8560 Four software readable jumpers for development use DMC CIRCUIT BOARD The DMC is a custom 4 layer circuit board It has the...

Page 102: ...32 interface See Table 10 3 for the pin assignments P3 The 16 pin COP JTAG interface header allows software development to the MPC8560 pro cessor Refer to Table 10 4 for the pin assignments SPARE ENET BOOT JP3 JP4 CPLD JTAG COP JTAG PORT 1 PORT 0 1 2 1 2 1 2 10002939 00 C3 C4 C5 C7 C10 C11 C13 C12 C1 F1 U2 CR1 CR2 CR3 CR4 R23 R24 R25 R26 R27 R28 R29 R30 R3 R4 R5 R6 R1 R2 U5 U3 R9 R10 R11 R12 R13 R...

Page 103: ...nnector Pin Assignments Pin Signal Pin Signal 1 3 3 V 2 CPLD_TCK 3 Ground 4 no connect 5 no connect 6 DMC_CS 7 DMC_OE 8 LWE0 9 LA18 10 LA17 11 LA16 12 LA15 13 LA14 14 LA13 15 LA12 16 LA11 17 LA10 18 LA9 19 LA8 20 LA7 21 LA6 22 LA5 23 LA4 24 LA3 25 LA2 26 LA1 27 LA0 28 FLASH_D0 29 FLASH_D1 30 FLASH_D2 31 FLASH_D3 32 FLASH_D4 33 FLASH_D5 34 FLASH_D6 35 FLASH_D7 36 SCC1_RS232_TX 37 SCC1_RS232_RX 38 G...

Page 104: ...Data Out is an input to DMC and part of CPU JTAG interface CPU_TDI CPU Test Data In is a DMC output and part of CPU JTAG interface DEBUG_TRST CPU Test Reset is an output from DMC and part of CPU JTAG interface CPU_TMS CPU Test Mode Select is an output from DMC and part of CPU JTAG interface CPU_CKSTP_OUT Check Stop Out is an input to DMC used by the debug header CPLD_TDI PLD Test Data In is part o...

Page 105: ... available at the front panel P14 connector and DMC only one should be connected at any given time Connecting more than one serial port would create a conflict and the serial port may not operate correctly P3 JTAG COP The JTAG COP interface provides for boundary scan testing of the CPU and the Pm8560 This interface is compliant with the IEEE 1149 1 Standard Test Access Port TAP and Boundary Scan A...

Page 106: ...this signal acts as the input port for scan instructions and data CPU_TDO Test Data Output this signal acts as the output port for scan instructions and data CPU_TMS Test Mode Select this input signal is the test access port TAP controller mode signal P4 JTAG Chain Header Figure 10 5 DMC P4 JTAG Header Table 10 5 DMC P4 JTAG Header Pin Assignments CPLD_TCK Test Clock Input this is the clock input ...

Page 107: ...er posts See Fig 10 6 for the jumper and LED location on the DMC Reference the Jumper Settings JSR 0x18 on page 8 5 Figure 10 6 DMC Jumper JP1 The Ethernet configuration jumper pins 1 and 2 is not used on the Pm8560 JP2 A shunt on pins 3 and 4 selects the 8 bit ROM socket as the boot device So in order for the socket to provide boot code the DMC must be seated on the Pm8560 and the boot shunt must...

Page 108: ...the board from a rack while power is applied at risk of damage to the board Installing the DMC Card Use the following procedure to attach the DMC to the Pm8560 see Fig 10 7 for DMC loca tion 1 Remove the protective vinyl caps from the screws 2 Line up the screws with the holes on the bottom side of the Pm8560 3 Snap the PCB to PCB connectors together and secure the mounting screws through the stan...

Page 109: ...is properly oriented in the socket Caution When removing the socketed PLCC device always use the extraction tool designed specifically for that task Otherwise you risk damaging the PLCC device Be sure the system is not overheating SPARE ENET BOOT JP3 JP4 CPLD JTAG COP JTAG PORT 1 PORT 01 2 1 2 1 2 10002939 00 C3 C4 C5 C7 C10 C11 C13 C12 C1 F1 U2 CR1 CR2 CR3 CR4 R23 R24 R25 R26 R27 R28 R29 R30 R3 R...

Page 110: ...8006 US 44 131 475 7070 UK Figure 10 8 Serial Number and Product ID on Bottom Side Product Repair If you plan to return the board to Emerson Network Power for service visit http www emersonembeddedcomputing com contact productrepair html on the inter net or send e mail to serviceinfo artesyncp com to obtain a return merchandise authoriza tion RMA number We will ask you to list which items you are ...

Page 111: ...Network Power Embedded Computing Test and Repair Services Department 8310 Excelsior Drive Madison WI 53717 RMA ____________ Put the RMA number on the outside of the package so we can handle your problem effi ciently Our service department cannot accept material received without an RMA number ...

Page 112: ...Development Mezzanine Card Troubleshooting Pm8560 User s Manual 10006609 03 10 12 ...

Page 113: ...er entering a command re execute it simply by pressing the ENTER or RETURN key TFTP Boot Use the TFTP protocol to load application images via Ethernet into the Pm8560 s memory Auto Boot Store specific boot commands in the environment to be executed automatically after reset Flash Programming Write application images into flash via the U Boot command line One megabyte at the base of flash is reserv...

Page 114: ...ory initializa tion and if necessary invokes the command line Note that the U Boot monitor has the ability to time out while waiting for EREADY see Table 11 2 for default configuration set tings Hardware initialization Monitor command prompt U Boot 1 1 1 Aug 8 2007 11 04 55 Mon Ver 1 4 Motorola PowerPC ProcessorID 00000000 Rev SVR 80700020 PVR 80200020 Board Artesyn Technologies pm8560 PMC Module ...

Page 115: ...e base Initialize U Boot environment Initialize serial port per baudrate environment variable Set debug LED 0010 Determine all internal bus frequencies and display to console Initialize I2C bus 1 Set debug LED 0011 Initialize SDRAM clear per clearmem and config ECC Set debug LED 0100 Relocate U Boot to RAM Set debug LED 0101 Initialize Flash Initialize L2 cache Initialize PCI Monarch Enumerate PCI...

Page 116: ...itialized data and code in the top one megabyte of SDRAM The exact address varies with the amount of installed memory U Boot uses the area from 0x00000000 to 0x00004000 in SDRAM for the MPC8560 exception vector table and U Boot internal use Caution Any writes to these areas can cause unpredictable operation of the monitor Updating the Monitor A new feature of the Pm8560 is the ability to boot from...

Page 117: ... see Table 11 2 Pm8560 1 4 erase e1f80000 e1ffffff 5 Program the monitor into soldered flash bank 0 Pm8560 1 4 cp b fff00000 e1f80000 80000 If it is necessary to manually update the monitor use steps 6 through 8 to update flash bank 0 6 Unprotect the flash Pm8560 1 4 protect off bank 0 7 Erase the monitor region of soldered flash see Table 11 2 Pm8560 1 4 erase e0f80000 e0ffffff 8 Program the moni...

Page 118: ...hdog timer unless watchdog command is in the bootcmd environment The watchdog feature checks for a boot redirection failure and repairs the monitor if needed Set the watchdog to activate every seconds and boot your code If you need to disable this watchdog feature set the variable watchdog_disable to on The monrecovery command see page 11 21 checks if a boot redirection has occurred If so monrecov...

Page 119: ...ommand Syntax The monitor uses the following basic command syntax Command argument 1 argument N The command line accepts three different argument formats string numeric and symbolic All command arguments must be separated by spaces with the exception of argument flags which are described below Monitor commands that expect numeric arguments assume a hexadecimal base unless noted otherwise in docume...

Page 120: ...ues in the form struct BusComStruct unsigned long MagicLoc unsigned long Call Address The first is used for synchronization and the second is the entry address of the application The sequence of events used for loading an application is described below 1 The host board waits for the target this board to write the value 0x496D4F6B character string ImOk to MagicLoc to show that the target is initial...

Page 121: ...ition bootm addr arg bootp The bootp command boots an image via a network connection using the BootP TFTP pro tocol If loadaddress or bootfilenameis not specified the environment variables loadaddr and bootfile are used as the default Definition bootp loadAddress bootfilename bootv The bootv command checks the checksum on the primary image in flash and boots it if valid If it is not valid it check...

Page 122: ...ess or bootfilename is not specified the environment variables loadaddr and bootfile are used as the default The port used is defined by the ethport environment variable If all is selected for ethport the TFTP process will cycle through each port until a connection is found or all ports have failed Definition tftpboot loadAddress bootfilename MEMORY COMMANDS The memory commands allow you to manipu...

Page 123: ...st match the size of the object flag The a option searches for the absence of the specified pattern Definition find b w l a base_addr top_addr pattern Example In this example the find command is used to search for the 32 bit pattern 0x12345678 in the address range starting at 0x40000 and ending at 0x80000 find 1 40000 80000 12345678 Searching from 0x00040000 to 0x00080000 Match found data 0x123456...

Page 124: ... prompts for a new value at the selected address After a new value is entered pressing ENTER modifies the value in memory and then the new value is displayed The command line then prompts for a new value to be written at the same address Pressing ENTER with out entering a new value leaves the original value unchanged To exit the nm command enter a non valid hexadecimal value such as x followed by ...

Page 125: ... access the individual sectors as 0 through 127 cp The cp command can be used to copy data into the flash device For the cp command syn tax refer to page 11 11 erase The erase command erases the specified area of flash memory Definition Erase all of the sectors in the address range from start to end erase start end Erase all of the sectors SF first sector to SL last sector in flash bank N erase N ...

Page 126: ... on all of the flash sectors in the address range from start to end protect off start end Remove protection on all of the sectors SF first sector to SL last sector in flash bank N protect off N SF SL Remove protection on all of the sectors in flash bank N protect off bank N Remove protection on all of the sectors in all of the flash banks protect off all I2 C COMMANDS This section describes comman...

Page 127: ...00 bytes from offset 0x1800 of I2 C device 0x53 right shifted 7 bit address The 2 at the end of the offset is the length in bytes of the offset information sent to the device The serial EEPROMs all have two byte offset lengths The RTC has a one byte offset length The temperature sensors have zero byte offset lengths Definition imd2 chip address 0 1 2 of objects imm The imm command modifies the pri...

Page 128: ...monitor The environment parameter commands deal with the reading and writing of these parameters Refer to page 11 23 for a list of monitor environment variables printenv The printenv command displays all of the environment variables and their current values to the display Definition Print the values of all environment variables printenv Print the values of all environment variable exact match name...

Page 129: ...d unlocks the ROMs to allow user accessible writes srom_wp 00 TEST COMMANDS The commands described in this section perform diagnostic and memory tests diags The diags command runs the Power on Self test POST See Table 11 2 Definition diags mtest The mtest command performs a simple SDRAM read write test Definition mtest start end pattern um The um command is a destructive memory test Definition um ...

Page 130: ...e address offset for the memory commands base Sets the address offset for the memory commands to off base off bdinfo The bdinfo command displays the Board Information Structure Definition bdinfo coninfo The coninfo command displays the information for all available console devices Definition coninfo crc32 The crc32 command computes a CRC32 checksum on count bytes starting at address Definition crc...

Page 131: ...ocket soldered go The go command runs an application at address addr passing the optional argument arg to the called application Definition go addr arg help The help or command displays the online help Without arguments all commands are displayed with a short usage message for each To obtain more detailed information for a specific command enter the desired command as an argument Definition help c...

Page 132: ...e environment variables and serial number in NVRAM but do not update the monitor in soldered flash moninit serial noburn Initialize environment variables and serial number in NVRAM and copy the monitor from src_address into soldered flash moninit serial src_address Use the following command to install the monitor Definition For the primary image 0xE1F80000 moninit serial_num mon2init The mon2init ...

Page 133: ...how the header of PCI device bus device function pci header b d f Display the PCI configuration space CFG pci display b w l b d f address of objects Modify read and keep the CFG address pci next b w l b d f address Modify automatically increments the CFG address pci modify b w l b d f address Write to the CFG address pci write b w l b d f address value ping The ping command sends a ping over Ether...

Page 134: ... PCI bus and lists the base address of the devices Definition showpci sleep The sleep command executes a delay of N seconds Definition Delay execution for N seconds N is a decimal value sleep N version The version command displays the monitor s current version number Definition version watchdog The watchdog command sets the watchdog timer to a period in seconds specified by the variable watchdog_p...

Page 135: ...oboot bootfile Path to boot file on server used with TFTP set this to the path file bin to specify filename and location of the file to load clearmem on Select whether to clear unused SDRAM memory used by monitor is excluded on power up and reset Valid options on off gatewayip 0 0 0 0 Select the network gateway machine IP address ipaddr 0 0 0 0 Board IP address loadaddr 0x100000 Define the address...

Page 136: ...it for PCI EREADY signal before enumeration as a Monarch This only applies to power up enumeration when the board is a Monarch If not defined the default is on Valid options on off eready_wait Sets the EREADY wait time out value when the eready parameter is set to on This parameter takes a decimal value icache Enables the processor L1 cache instruction If not defined default is on Valid options on...

Page 137: ...onsists of two parts Magic number which is 0x12345670 number of sections Information for each section including the load address unsigned long the section size unsigned long and a checksum unsigned long that is the long word sum of the memory bytes of the data section Motorola S Record S Record download uses the standard Motorola S Record format This includes load address section size and checksum...

Page 138: ...Monitor Download Formats Pm8560 User s Manual 10006609 03 11 26 ...

Page 139: ...ctrostatic Discharge ETSI European Telecommunications Standards Institute FCC Federal Communications Commission FRU Field Replaceable Unit GbE Gigabit Ethernet GNU GNU s Not Unix GPL General Public License I2 C Inter integrated Circuit ICE In circuit Emulator IEC International Electrotechnical Commission JTAG Joint Test Action Group LED Light emitting Diode MAC Medium media Access Control controll...

Page 140: ...thorization RTC Real time Clock SDRAM Synchronous Dynamic Random Access Memory SO DIMM Small outline Dual In line Memory SPD Serial Presence Detect SROM Serial Read Only Memory TBD To Be Determined TDM Time Division Multiplexed TSA Time Slot Assignment UART Universal Asynchronous Receiver transmitter UL Underwriters Laboratories USB Universal Serial Bus ...

Page 141: ...2 installation 10 8 jumpers 10 7 device select signal PCI 7 8 E E1 T1 J1 6 1 to MPC8560 options 6 2 EEPROM I2C 4 2 enumeration ready signal PCI 7 8 environment parameter commands monitor 11 16 environment variables 11 7 11 23 equipment for setup 2 5 ESD prevention 2 1 Ethernet address 9 1 Emerson identifier 9 1 transceivers 9 1 F features general 1 1 figures list of iii vii file load command tftpb...

Page 142: ... pin assignments 6 6 P17 serial port pin assignments 5 1 P20 Ethernet pin assignments 9 2 parity error signal PCI 7 9 parity signal PCI 7 9 PCI interrupts 7 6 reset operations 7 5 vital product data 7 2 power requirements 2 6 product code Ethernet 9 1 product repair 2 11 10 10 programmable logic device PLD 8 1 protection circuitry 6 2 R real time clock overview 1 1 references and manuals 1 8 regis...

Page 143: ...ology 1 7 test commands monitor 11 17 test data input signal PCI 7 9 test data output signal PCI 7 9 test mode select signal PCI 7 9 test reset signal PCI 7 9 time division multiplexor TDM 6 1 timing general purpose CPU 3 4 system synchronizer control register 8 15 troubleshooting general 2 9 10 9 monitor 11 24 U UL certifications 1 7 V vital product data 7 2 ...

Page 144: ...Index continued Pm8560 User s Manual 10006609 03 i 4 ...

Page 145: ...___________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ...

Page 146: ...wer and the Emerson Network Power logo are trademarks and service marks of Emerson Electric Co 2007 Emerson Electric Co Emerson Network Power The global leader in enabling Business Critical Continuity AC Power Systems Connectivity DC Power Systems Embedded Computing Embedded Power Integrated Cabinet Solutions Outside Plant Power Switching Controls Precision Cooling Services Site Monitoring Surge S...

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