32
7679H–CAN–08/08
AT90CAN32/64/128
4.5.6
External Memory Control Register A – XMCRA
• Bit 7 – SRE: External SRAM/XMEM Enable
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8,
ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin
direction settings in the respective data direction registers. Writing SRE to zero, disables the
External Memory Interface and the normal pin and data direction settings are used. Note that
when the XMEM interface is disabled, the address space above the internal SRAM boundary is
not mapped into the internal SRAM.
• Bit 6..4 – SRL2, SRL1, SRL0: Wait-state Sector Limit
It is possible to configure different wait-states for different External Memory addresses. The
external memory address space can be divided in two sectors that have separate wait-state bits.
The SRL2, SRL1, and SRL0 bits select the split of the sectors, see
and
. By
default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address
space is treated as one sector. When the entire SRAM address space is configured as one sec-
tor, the wait-states are configured by the SRW11 and SRW10 bits.
Note:
1. See
for “XMem start” setting.
Bit
7
6
5
4
3
2
1
0
SRE
SRL2
SRL1
SRL0
SRW11
SRW10
SRW01
SRW00
XMCRA
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Table 4-3.
Sector limits with different settings of SRL2..0
SRL2
SRL1
SRL0
Sector
Addressing
0
0
0
Lower sector
N/A
Upper sector
- 0xFFFF
0
0
1
Lower sector
- 0x1FFF
Upper sector
0x2000 - 0xFFFF
0
1
0
Lower sector
- 0x3FFF
Upper sector
0x4000 - 0xFFFF
0
1
1
Lower sector
- 0x5FFF
Upper sector
0x6000 - 0xFFFF
1
0
0
Lower sector
- 0x7FFF
Upper sector
0x8000 - 0xFFFF
1
0
1
Lower sector
- 0x9FFF
Upper sector
0xA000 - 0xFFFF
1
1
0
Lower sector
- 0xBFFF
Upper sector
0xC000 - 0xFFFF
1
1
1
Lower sector
- 0xDFFF
Upper sector
0xE000 - 0xFFFF