261
7679H–CAN–08/08
AT90CAN32/64/128
• Bit 7:4 – MOBNB3:0: MOb Number
Selection of the MOb number, the available numbers are from 0 to 14.
• Bit 3 – AINC: Auto Increment of the FIFO CAN Data Buffer Index (Active Low)
– 0 - auto increment of the index (default value).
– 1- no auto increment of the index.
• Bit 2:0 – INDX2:0: FIFO CAN Data Buffer Index
Byte location of the CAN data byte into the FIFO for the defined MOb.
19.11 MOb Registers
The MOb registers has
no
initial (default) value after RESET.
19.11.1
CAN MOb Status Register - CANSTMOB
• Bit 7 – DLCW: Data Length Code Warning
The incoming message does not have the DLC expected. Whatever the frame type, the DLC
field of the CANCDMOB register is updated by the received DLC.
• Bit 6 – TXOK: Transmit OK
This flag can generate an interrupt. It must be cleared using a read-modify-write software routine
on the whole CANSTMOB register.
The communication enabled by transmission is completed.
TxOK rises at the end of EOF field and then, the MOb is disabled (the corresponding ENMOB-bit
of CANEN registers is cleared). When the controller is ready to send a frame, if two or more
message objects are enabled as producers, the lower MOb index is supplied first.
• Bit 5 – RXOK: Receive OK
This flag can generate an interrupt. It must be cleared using a read-modify-write software routine
on the whole CANSTMOB register.
The communication enabled by reception is completed.
RxOK rises at the end of the 6
th
bit of EOF field and then, the MOb is disabled (the correspond-
ing ENMOB-bit of CANEN registers is cleared). In case of two or more message object reception
hits, the lower MOb index is updated first.
• Bit 4 – BERR: Bit Error (Only in Transmission)
This flag can generate an interrupt. It must be cleared using a read-modify-write software routine
on the whole CANSTMOB register.
The bit value monitored is different from the bit value sent.
Exceptions: the monitored recessive bit sent as a dominant bit during the arbitration field and the
acknowledge slot detecting a dominant bit during the sending of an error frame.
Bit
7
6
5
4
3
2
1
0
DLCW
TXOK
RXOK
BERR
SERR
CERR
FERR
AERR
CANSTMOB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
-
-
-
-
-
-
-
-
