162
7679H–CAN–08/08
AT90CAN32/64/128
• Description of wake up from Power-save mode when the timer is clocked asynchronously:
When the interrupt condition is met, the wake up process is started on the following cycle of
the timer clock, that is, the timer is always advanced by at least one before the processor can
read the counter value. After wake-up, the MCU is halted for four cycles, it executes the
interrupt routine, and resumes execution from the instruction following SLEEP.
• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect
result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be
done through a register synchronized to the internal I/O clock domain. Synchronization takes
place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O
clock (clk
I/O
) again becomes active, TCNT2 will read as the previous value (before entering
sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from
Power-save mode is essentially unpredictable, as it depends on the wake-up time. The
recommended procedure for reading TCNT2 is thus as follows:
a.
Write any value to either of the registers OCR2A or TCCR2A.
b.
Wait for the corresponding Update Busy Flag to be cleared.
c.
Read TCNT2.
• During asynchronous operation, the synchronization of the interrupt flags for the
asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore
advanced by at least one before the processor can read the timer value causing the setting of
the interrupt flag. The Output Compare pin is changed on the timer clock and is not
synchronized to the processor clock.
14.10.3
Timer/Counter2
Interrupt Mask Register – TIMSK2
• Bit 7..2 – Reserved Bits
These bits are reserved for future use.
• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable
When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the
Timer/Counter2 Interrupt Flag Register – TIFR2.
• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt
Flag Register – TIFR2.
14.10.4
Timer/Counter2 Interrupt Flag Register – TIFR2
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
–
OCIE2A
TOIE2
TIMSK2
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
–
OCF2A
TOV2
TIFR2
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
