Atmel AVR AT90CAN128, Manual

Page: 377 / 428

377
7679H–CAN–08/08
AT90CAN32/64/128
Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
11 t
RHDX
Data Hold After RD High 0 0 ns
12 t
RLRH
RD Pulse Width 235 1.0 t
CLCL
– 15 ns
13 t
DVWL
Data Setup to WR Low 105 0.5 t
CLCL
– 20
(1)
ns
14 t
WHDX
Data Hold After WR High 235 1.0 t
CLCL
– 15 ns
15 t
DVWH
Data Valid to WR High 250 1.0 t
CLCL
ns
16 t
WLWH
WR Pulse Width 235 1.0 t
CLCL
– 15 ns
Table 26-11. External Data Memory Characteristics, V
CC
= 2.7 - 5.5 Volts, No Wait-state (Continued)
Symbol Parameter
4 MHz Oscillator Variable Oscillator
Unit
Min. Max. Min. Max.
Table 26-12. External Data Memory Characteristics, V
CC
= 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1
Symbol Parameter
4 MHz Oscillator Variable Oscillator
Unit
Min. Max. Min. Max.
0 1/t
CLCL
Oscillator Frequency 0.0 8 MHz
10 t
RLDV
Read Low to Data Valid 440 2.0 t
CLCL
– 60 ns
12 t
RLRH
RD Pulse Width 485 2.0 t
CLCL
– 15 ns
15 t
DVWH
Data Valid to WR High 500 2.0 t
CLCL
ns
16 t
WLWH
WR Pulse Width 485 2.0 t
CLCL
– 15 ns
Table 26-13. External Data Memory Characteristics, V
CC
= 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0
Symbol Parameter
4 MHz Oscillator Variable Oscillator
Unit
Min. Max. Min. Max.
0 1/t
CLCL
Oscillator Frequency 0.0 8 MHz
10 t
RLDV
Read Low to Data Valid 690 3.0 t
CLCL
– 60 ns
12 t
RLRH
RD Pulse Width 735 3.0 t
CLCL
– 15 ns
15 t
DVWH
Data Valid to WR High 750 3.0 t
CLCL
ns
16 t
WLWH
WR Pulse Width 735 3.0 t
CLCL
– 15 ns
Table 26-14. External Data Memory Characteristics, V
CC
= 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1
Symbol Parameter
4 MHz Oscillator Variable Oscillator
Unit
Min. Max. Min. Max.
0 1/t
CLCL
Oscillator Frequency 0.0 8 MHz
10 t
RLDV
Read Low to Data Valid 690 3.0 t
CLCL
– 60 ns
12 t
RLRH
RD Pulse Width 735 3.0 t
CLCL
– 15 ns