259
7679H–CAN–08/08
AT90CAN32/64/128
• Bit 7– Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT3 is written.
• Bit 6:4 – PHS22:0: Phase Segment 2
This phase is used to compensate for phase edge errors. This segment may be shortened by
the re-synchronization jump width. PHS2[2..0] shall be
≥
1 and
≤
PHS1[2..0] (c.f.
and
Section 19.4.3 ”Baud Rate” on page 242
).
• Bit 3:1 – PHS12:0: Phase Segment 1
This phase is used to compensate for phase edge errors. This segment may be lengthened by
the re-synchronization jump width.
• Bit 0 – SMP: Sample Point(s)
This option allows to filter possible noise on TxCAN input pin.
– 0 - the sampling will occur once at the user configured sampling point -
SP
.
– 1 - with three-point sampling configuration the first sampling will occur two
T
clk
IO
clocks before the user configured sampling point -
SP
, again at one
T
clk
IO
clock
before
SP
and finally at
SP
. Then the bit level will be determined by a majority vote of
the three samples.
‘SMP=1’ configuration is not compatible with ‘BRP[5:0]=0’ because TQ =
T
clk
IO
.
If BRP = 0, SMP must be cleared.
19.10.11 CAN Timer Control Register - CANTCON
• Bit 7:0 – TPRSC7:0: CAN Timer Prescaler
Prescaler for the CAN timer upper counter range 0 to 255. It provides the clock to the CAN timer
if the CAN controller is enabled.
T
clk
CANTIM
=
T
clk
IO
x 8 x (CANTCON [7:0] + 1)
19.10.12 CAN Timer Registers - CANTIML and CANTIMH
• Bits 15:0 - CANTIM15:0: CAN Timer Count
CAN timer counter range 0 to 65,535.
Tphs2 = Tscl x (PHS2 [2:0] + 1)
Tphs1 = Tscl x (PHS1 [2:0] + 1)
Bit
7
6
5
4
3
2
1
0
TPRSC7
TPRSC6
TPRSC5
TPRSC4
TPRSC3
TPRSC2
TRPSC1
TPRSC0
CANTCON
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CANTIM7
CANTIM6
CANTIM5
CANTIM4
CANTIM3
CANTIM2
CANTIM1 CANTIM0 CANTIML
CANTIM15 CANTIM14 CANTIM13 CANTIM12 CANTIM11 CANTIM10 CANTIM9 CANTIM8 CANTIMH
Bit
15
14
13
12
11
10
9
8
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
