135
7679H–CAN–08/08
AT90CAN32/64/128
Figure 13-12.
Timer/Counter Timing Diagram, no Prescaling
shows the same timing data, but with the prescaler enabled.
Figure 13-13.
Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
13.11 16-bit Timer/Counter Register Description
13.11.1
Timer/Counter1 Control Register A – TCCR1A
13.11.2
Timer/Counter3 Control Register A – TCCR3A
TOVn
(FPWM)
and ICFn
(if used
as TOP)
OCRnx
(Update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
TOP - 1
TOP - 2
Old OCRnx Value
New OCRnx Value
TOP - 1
TOP
BOTTOM
1
clk
Tn
(clk
I/O
/1)
clk
I/O
TOVn
(FPWM)
and ICFn
(if used
as TOP)
OCRnx
(Update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
TOP - 1
TOP - 2
Old OCRnx Value
New OCRnx Value
TOP - 1
TOP
BOTTOM
1
clk
I/O
clk
Tn
(clk
I/O
/8)
Bit
7
6
5
4
3
2
1
0
COM1A1
COM1A0
COM1B1
COM1B0
COM1C1
COM1C0
WGM11
WGM10
TCCR1A
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
COM3A1
COM3A0
COM3B1
COM3B0
COM3C1
COM3C0
WGM31
WGM30
TCCR3A
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
